From: Ville Syrjälä
Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for
all the relevant underrun bits, so in order to keep the error interrupt
enabled, we need to have underrun reporting enabled on all PCH
transocders. Currently we leave the
On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for
> all the relevant underrun bits, so in order to keep the error interrupt
> enabled, we need to have
On Thu, Oct 29, 2015 at 12:36:34PM -0700, Jesse Barnes wrote:
> On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for
> > all the relevant underrun bits, so