Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
On Thu, 20 Apr 2023, Mika Kahola wrote: > Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. > > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f7720acaf58c..4231ba98f075 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct > intel_encoder *encoder, > val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > > /* TODO: HDMI FRL */ > - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ > - val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : > 0; > + /* DP2.0 10G and 20G rates enable MPLLA*/ > + if (crtc_state->port_clock == 100 || crtc_state->port_clock == > 200) Please use intel_dp_is_uhbr(). > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLA : 0; > + else > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), >XELPDP_LANE1_PHY_CLOCK_SELECT | > XELPDP_FORWARD_CLOCK_UNGATE | -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
> -Original Message- > From: Intel-gfx On Behalf Of Mika > Kahola > Sent: Thursday, April 20, 2023 6:11 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates > use MPLLA > > Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. Need to fix a typo here. It will be 10G and 20G. Regards, Animesh > > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f7720acaf58c..4231ba98f075 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct > intel_encoder *encoder, > val |= > XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > > /* TODO: HDMI FRL */ > - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ > - val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > + /* DP2.0 10G and 20G rates enable MPLLA*/ > + if (crtc_state->port_clock == 100 || crtc_state->port_clock == > 200) > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLA : 0; > + else > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), >XELPDP_LANE1_PHY_CLOCK_SELECT | > XELPDP_FORWARD_CLOCK_UNGATE | > -- > 2.34.1
Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
> -Original Message- > From: Intel-gfx On Behalf Of Mika > Kahola > Sent: Thursday, April 20, 2023 6:11 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates > use MPLLA > > Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. > > Signed-off-by: Mika Kahola > --- Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f7720acaf58c..4231ba98f075 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct > intel_encoder *encoder, > val |= > XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > > /* TODO: HDMI FRL */ > - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ > - val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > + /* DP2.0 10G and 20G rates enable MPLLA*/ > + if (crtc_state->port_clock == 100 || crtc_state->port_clock == > 200) > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLA : 0; > + else > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), >XELPDP_LANE1_PHY_CLOCK_SELECT | > XELPDP_FORWARD_CLOCK_UNGATE | > -- > 2.34.1
Re: [Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
On Thu, Apr 20, 2023 at 03:40:43PM +0300, Mika Kahola wrote: > Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. > Reviewed-by: Radhakrishna Sripada - Radhakrishna(RK) Sripada > Signed-off-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index f7720acaf58c..4231ba98f075 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct > intel_encoder *encoder, > val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); > > /* TODO: HDMI FRL */ > - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ > - val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : > 0; > + /* DP2.0 10G and 20G rates enable MPLLA*/ > + if (crtc_state->port_clock == 100 || crtc_state->port_clock == > 200) > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLA : 0; > + else > + val |= crtc_state->cx0pll_state.ssc_enabled ? > XELPDP_SSC_ENABLE_PLLB : 0; > > intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), >XELPDP_LANE1_PHY_CLOCK_SELECT | > XELPDP_FORWARD_CLOCK_UNGATE | > -- > 2.34.1 >
[Intel-gfx] [PATCH 06/13] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index f7720acaf58c..4231ba98f075 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2340,8 +2340,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); /* TODO: HDMI FRL */ - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ - val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; + /* DP2.0 10G and 20G rates enable MPLLA*/ + if (crtc_state->port_clock == 100 || crtc_state->port_clock == 200) + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; + else + val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | -- 2.34.1
