Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-06 Thread Manasi Navare
On Fri, Sep 02, 2016 at 04:00:20PM +0300, Mika Kahola wrote: > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower lane count

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-06 Thread Manasi Navare
On Fri, Sep 02, 2016 at 03:49:02PM +0300, David Weinehall wrote: > On Thu, Sep 01, 2016 at 03:08:16PM -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-06 Thread Manasi Navare
On Fri, Sep 02, 2016 at 03:03:22PM +0300, David Weinehall wrote: > On Thu, Sep 01, 2016 at 03:08:16PM -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-02 Thread Jim Bride
On Fri, Sep 02, 2016 at 07:52:53PM +, Pandiyan, Dhinakaran wrote: > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower lane

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-02 Thread Pandiyan, Dhinakaran
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with Channel

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-02 Thread Mika Kahola
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with Channel

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-02 Thread David Weinehall
On Thu, Sep 01, 2016 at 03:08:16PM -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with

Re: [Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-02 Thread David Weinehall
On Thu, Sep 01, 2016 at 03:08:16PM -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with

[Intel-gfx] [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-01 Thread Manasi Navare
According to the DisplayPort Spec, in case of Clock Recovery failure the link training sequence should fall back to the lower link rate followed by lower lane count until CR succeeds. On CR success, the sequence proceeds with Channel EQ. In case of Channel EQ failures, it should fallback to lower