On Fri, Sep 02, 2016 at 04:08:27PM +0300, Mika Kahola wrote:
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > While configuring the pipe during modeset, it should loop
> > starting from max clock and max lane count reducing the
> > lane count and clock in each iteration until the reque
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> While configuring the pipe during modeset, it should loop
> starting from max clock and max lane count reducing the
> lane count and clock in each iteration until the requested mode
> rate is less than or equal to available link BW.
>
> Sig
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> While configuring the pipe during modeset, it should loop
> starting from max clock and max lane count reducing the
> lane count and clock in each iteration until the requested mode
> rate is less than or equal to available link BW.
>
> Sig
While configuring the pipe during modeset, it should loop
starting from max clock and max lane count reducing the
lane count and clock in each iteration until the requested mode
rate is less than or equal to available link BW.
Signed-off-by: Manasi Navare
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drivers/gpu/drm/i915/intel_dp.c | 9
