On Mon, Apr 28, 2014 at 05:54:24PM +0300, Imre Deak wrote:
On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
From: Chon Ming Lee chon.ming@intel.com
During cold boot, the display controller needs to deassert the common
lane reset. Only do it once during
On Wed, 2014-04-09 at 13:28 +0300, ville.syrj...@linux.intel.com wrote:
From: Chon Ming Lee chon.ming@intel.com
During cold boot, the display controller needs to deassert the common
lane reset. Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.
Besides, assert the
From: Chon Ming Lee chon.ming@intel.com
During cold boot, the display controller needs to deassert the common
lane reset. Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.
Besides, assert the common lane reset when disable pll. This still
to be determined whether need to do
