Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-06-02 Thread Kumar, Shobhit 

On 5/26/2014 6:22 PM, Jani Nikula wrote:

On Mon, 19 May 2014, Imre Deak imre.d...@intel.com wrote:

So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the initial modeset,
where the BIOS-programmed values happened to work, but after resuming
from s0ix these registers are reset and failing to program them results
in a blank screen.


Shobhit, this was already merged, did you have a chance to test it?



Sorry just saw this today. Yeah I have pulled this in my test tree and 
suspend/resume was working perfect, but then I was not doing display 
powergate. In the internal code though S0ix was implemented. I will 
double check if the internal code had correct opcodes and somehow wrong 
opcodes trickled into intel-gfx. As of now looks okay and works fine for me.


Regards
Shobhit


Jani.




Signed-off-by: Imre Deak imre.d...@intel.com
---
  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index f3909d5..01d841e 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
  {
u32 val = 0;
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
reg, val);
return val;
  }

  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  {
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
reg, val);
  }
--
1.8.4

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-26 Thread Jani Nikula 
On Mon, 19 May 2014, Imre Deak imre.d...@intel.com wrote:
 So far we used the wrong opcodes to access the DSI registers, so the
 register writes during DSI programming didn't actually succeed and left
 the registers unchanged. This wasn't a problem for the initial modeset,
 where the BIOS-programmed values happened to work, but after resuming
 from s0ix these registers are reset and failing to program them results
 in a blank screen.

Shobhit, this was already merged, did you have a chance to test it?

Jani.



 Signed-off-by: Imre Deak imre.d...@intel.com
 ---
  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
 b/drivers/gpu/drm/i915/intel_sideband.c
 index f3909d5..01d841e 100644
 --- a/drivers/gpu/drm/i915/intel_sideband.c
 +++ b/drivers/gpu/drm/i915/intel_sideband.c
 @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
 u16 reg, u32 value,
  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
  {
   u32 val = 0;
 - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
 + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
   reg, val);
   return val;
  }
  
  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  {
 - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
 + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
   reg, val);
  }
 -- 
 1.8.4

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[Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-19 Thread Imre Deak 
So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the initial modeset,
where the BIOS-programmed values happened to work, but after resuming
from s0ix these registers are reset and failing to program them results
in a blank screen.

Signed-off-by: Imre Deak imre.d...@intel.com
---
 drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index f3909d5..01d841e 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
 {
u32 val = 0;
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
reg, val);
return val;
 }
 
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 {
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
reg, val);
 }
-- 
1.8.4

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-19 Thread Jesse Barnes 
On Mon, 19 May 2014 11:41:18 +0300
Imre Deak imre.d...@intel.com wrote:

 So far we used the wrong opcodes to access the DSI registers, so the
 register writes during DSI programming didn't actually succeed and left
 the registers unchanged. This wasn't a problem for the initial modeset,
 where the BIOS-programmed values happened to work, but after resuming
 from s0ix these registers are reset and failing to program them results
 in a blank screen.
 
 Signed-off-by: Imre Deak imre.d...@intel.com
 ---
  drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
 b/drivers/gpu/drm/i915/intel_sideband.c
 index f3909d5..01d841e 100644
 --- a/drivers/gpu/drm/i915/intel_sideband.c
 +++ b/drivers/gpu/drm/i915/intel_sideband.c
 @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, 
 u16 reg, u32 value,
  u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
  {
   u32 val = 0;
 - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
 + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
   reg, val);
   return val;
  }
  
  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  {
 - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
 + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
   reg, val);
  }

Nice find... is this documented somewhere so we can put a reference
in?  Or is it in the Punit HAS somewhere already and we just missed it?

Thanks,
-- 
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-19 Thread Imre Deak 
On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
 On Mon, 19 May 2014 11:41:18 +0300
 Imre Deak imre.d...@intel.com wrote:
 
  So far we used the wrong opcodes to access the DSI registers, so the
  register writes during DSI programming didn't actually succeed and left
  the registers unchanged. This wasn't a problem for the initial modeset,
  where the BIOS-programmed values happened to work, but after resuming
  from s0ix these registers are reset and failing to program them results
  in a blank screen.
  
  Signed-off-by: Imre Deak imre.d...@intel.com
  ---
   drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)
  
  diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
  b/drivers/gpu/drm/i915/intel_sideband.c
  index f3909d5..01d841e 100644
  --- a/drivers/gpu/drm/i915/intel_sideband.c
  +++ b/drivers/gpu/drm/i915/intel_sideband.c
  @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private 
  *dev_priv, u16 reg, u32 value,
   u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
   {
  u32 val = 0;
  -   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
  +   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
  reg, val);
  return val;
   }
   
   void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
   {
  -   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
  +   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
  reg, val);
   }
 
 Nice find... is this documented somewhere so we can put a reference
 in?  Or is it in the Punit HAS somewhere already and we just missed it?

I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
this file with a reference to it.

--Imre



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Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-19 Thread Jesse Barnes 
On Mon, 19 May 2014 18:10:18 +0300
Imre Deak imre.d...@intel.com wrote:

 On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
  On Mon, 19 May 2014 11:41:18 +0300
  Imre Deak imre.d...@intel.com wrote:
  
   So far we used the wrong opcodes to access the DSI registers, so the
   register writes during DSI programming didn't actually succeed and left
   the registers unchanged. This wasn't a problem for the initial modeset,
   where the BIOS-programmed values happened to work, but after resuming
   from s0ix these registers are reset and failing to program them results
   in a blank screen.
   
   Signed-off-by: Imre Deak imre.d...@intel.com
   ---
drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
   
   diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
   b/drivers/gpu/drm/i915/intel_sideband.c
   index f3909d5..01d841e 100644
   --- a/drivers/gpu/drm/i915/intel_sideband.c
   +++ b/drivers/gpu/drm/i915/intel_sideband.c
   @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private 
   *dev_priv, u16 reg, u32 value,
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
{
 u32 val = 0;
   - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
   + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
 reg, val);
 return val;
}

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 
   val)
{
   - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
   + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
 reg, val);
}
  
  Nice find... is this documented somewhere so we can put a reference
  in?  Or is it in the Punit HAS somewhere already and we just missed it?
 
 I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
 this file with a reference to it.

Cool, this one has my
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
then too.

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing

2014-05-19 Thread Daniel Vetter 
On Mon, May 19, 2014 at 08:33:16AM -0700, Jesse Barnes wrote:
 On Mon, 19 May 2014 18:10:18 +0300
 Imre Deak imre.d...@intel.com wrote:
 
  On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
   On Mon, 19 May 2014 11:41:18 +0300
   Imre Deak imre.d...@intel.com wrote:
   
So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the initial modeset,
where the BIOS-programmed values happened to work, but after resuming
from s0ix these registers are reset and failing to program them results
in a blank screen.

Signed-off-by: Imre Deak imre.d...@intel.com
---
 drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index f3909d5..01d841e 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private 
*dev_priv, u16 reg, u32 value,
 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
 {
u32 val = 0;
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, 
SB_MRD_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, 
SB_CRRDDA_NP,
reg, val);
return val;
 }
 
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 
val)
 {
-   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, 
SB_MWR_NP,
+   vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, 
SB_CRWRDA_NP,
reg, val);
 }
   
   Nice find... is this documented somewhere so we can put a reference
   in?  Or is it in the Punit HAS somewhere already and we just missed it?
  
  I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
  this file with a reference to it.
 
 Cool, this one has my
 Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
 then too.

Both patches merged, thanks.
-Daniel
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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