On Tue, Feb 14, 2023 at 12:47:23PM -0800, Dixit, Ashutosh wrote:
> On Tue, 14 Feb 2023 06:51:37 -0800, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Mon, Feb 13, 2023 at 01:00:48PM -0800, Ashutosh Dixit wrote:
> > > Previous documentation suggested that the PL1 power limit is always
> > >
On Tue, 14 Feb 2023 06:51:37 -0800, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Mon, Feb 13, 2023 at 01:00:48PM -0800, Ashutosh Dixit wrote:
> > Previous documentation suggested that the PL1 power limit is always enabled
> > in HW. However we now find this not to be the case on some platforms (such
>
On Mon, Feb 13, 2023 at 01:00:48PM -0800, Ashutosh Dixit wrote:
> Previous documentation suggested that the PL1 power limit is always enabled
> in HW. However we now find this not to be the case on some platforms (such
> as ATSM). Therefore enable the PL1 power limit (by setting the enable bit)
>
Previous documentation suggested that the PL1 power limit is always enabled
in HW. However we now find this not to be the case on some platforms (such
as ATSM). Therefore enable the PL1 power limit (by setting the enable bit)
when writing the PL1 limit value to HW.
Bspec: 51864
Signed-off-by:
Previous documentation suggested that the PL1 power limit is always enabled
in HW. However we now find this not to be the case on some platforms (such
as ATSM). Therefore enable the PL1 power limit (by setting the enable bit)
when writing the PL1 limit value to HW.
Bspec: 51864
Signed-off-by:
