Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

2019-12-30 Thread Chris Wilson
Quoting Imre Deak (2019-12-30 19:20:36) > On Mon, Dec 30, 2019 at 10:53:21AM +, Chris Wilson wrote: > > Quoting Imre Deak (2019-12-27 23:51:46) > > > Currently the start address of a UV plane in a semiplanar YUV FB is tile > > > size (4kB) aligned. I noticed, that enforcing only this alignment

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

2019-12-30 Thread Imre Deak
On Mon, Dec 30, 2019 at 10:53:21AM +, Chris Wilson wrote: > Quoting Imre Deak (2019-12-27 23:51:46) > > Currently the start address of a UV plane in a semiplanar YUV FB is tile > > size (4kB) aligned. I noticed, that enforcing only this alignment leads > > oddly to random memory corruptions on

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

2019-12-30 Thread Chris Wilson
Quoting Imre Deak (2019-12-27 23:51:46) > Currently the start address of a UV plane in a semiplanar YUV FB is tile > size (4kB) aligned. I noticed, that enforcing only this alignment leads > oddly to random memory corruptions on TGL while scanning out Y-tiled > FBs. This issue can be easily

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned

2019-12-27 Thread Imre Deak
Currently the start address of a UV plane in a semiplanar YUV FB is tile size (4kB) aligned. I noticed, that enforcing only this alignment leads oddly to random memory corruptions on TGL while scanning out Y-tiled FBs. This issue can be easily reproduced with a UV plane that is not aligned to the