Re: [Intel-gfx] [PATCH 22/36] drm/i915: Move rps worker to intel_gt_pm.c

2018-03-16 Thread Sagar Arun Kamble 



On 3/14/2018 3:07 PM, Chris Wilson wrote:

The RPS worker exists to do the bidding of the GT powermanagement, so
move it from i915_irq to intel_gt_pm.c where it can be hidden from the
rest of the world. The goal being that the RPS worker is the one true
way though which all RPS updates are coordinated.

Signed-off-by: Chris Wilson 

Reviewed-by: Sagar Arun Kamble 

---
  drivers/gpu/drm/i915/i915_drv.h|   1 -
  drivers/gpu/drm/i915/i915_irq.c| 141 
  drivers/gpu/drm/i915/i915_sysfs.c  |  38 ++--
  drivers/gpu/drm/i915/intel_gt_pm.c | 186 ++---
  drivers/gpu/drm/i915/intel_gt_pm.h |   1 -
  5 files changed, 162 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5c10acf767a8..a57b20f95cdc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3406,7 +3406,6 @@ extern void i915_redisable_vga(struct drm_i915_private 
*dev_priv);
  extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
  extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
  extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
-extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
  extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  bool enable);
  
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c

index f815da0dd991..d9cf4f81979e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1130,145 +1130,6 @@ static void notify_ring(struct intel_engine_cs *engine)
trace_intel_engine_notify(engine, wait);
  }
  
-static void vlv_c0_read(struct drm_i915_private *dev_priv,

-   struct intel_rps_ei *ei)
-{
-   ei->ktime = ktime_get_raw();
-   ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
-   ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
-}
-
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
-{
-   memset(_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
-}
-
-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
-{
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   const struct intel_rps_ei *prev = >ei;
-   struct intel_rps_ei now;
-   u32 events = 0;
-
-   if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
-   return 0;
-
-   vlv_c0_read(dev_priv, );
-
-   if (prev->ktime) {
-   u64 time, c0;
-   u32 render, media;
-
-   time = ktime_us_delta(now.ktime, prev->ktime);
-
-   time *= dev_priv->czclk_freq;
-
-   /* Workload can be split between render + media,
-* e.g. SwapBuffers being blitted in X after being rendered in
-* mesa. To account for this we need to combine both engines
-* into our activity counter.
-*/
-   render = now.render_c0 - prev->render_c0;
-   media = now.media_c0 - prev->media_c0;
-   c0 = max(render, media);
-   c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
-
-   if (c0 > time * rps->up_threshold)
-   events = GEN6_PM_RP_UP_THRESHOLD;
-   else if (c0 < time * rps->down_threshold)
-   events = GEN6_PM_RP_DOWN_THRESHOLD;
-   }
-
-   rps->ei = now;
-   return events;
-}
-
-static void gen6_pm_rps_work(struct work_struct *work)
-{
-   struct drm_i915_private *dev_priv =
-   container_of(work, struct drm_i915_private, gt_pm.rps.work);
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   bool client_boost = false;
-   int new_delay, adj, min, max;
-   u32 pm_iir = 0;
-
-   spin_lock_irq(_priv->irq_lock);
-   if (rps->interrupts_enabled) {
-   pm_iir = fetch_and_zero(>pm_iir);
-   client_boost = atomic_read(>num_waiters);
-   }
-   spin_unlock_irq(_priv->irq_lock);
-
-   /* Make sure we didn't queue anything we're not going to process. */
-   WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
-   if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
-   goto out;
-
-   mutex_lock(>lock);
-
-   pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
-
-   adj = rps->last_adj;
-   new_delay = rps->cur_freq;
-   min = rps->min_freq_softlimit;
-   max = rps->max_freq_softlimit;
-   if (client_boost)
-   max = rps->max_freq;
-   if (client_boost && new_delay < rps->boost_freq) {
-   new_delay = rps->boost_freq;
-   adj = 0;
-   } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
-   if (adj > 0)
-   adj *= 2;
-   else /* CHV needs even encode values */
-   adj =

[Intel-gfx] [PATCH 22/36] drm/i915: Move rps worker to intel_gt_pm.c

2018-03-14 Thread Chris Wilson 
The RPS worker exists to do the bidding of the GT powermanagement, so
move it from i915_irq to intel_gt_pm.c where it can be hidden from the
rest of the world. The goal being that the RPS worker is the one true
way though which all RPS updates are coordinated.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h|   1 -
 drivers/gpu/drm/i915/i915_irq.c| 141 
 drivers/gpu/drm/i915/i915_sysfs.c  |  38 ++--
 drivers/gpu/drm/i915/intel_gt_pm.c | 186 ++---
 drivers/gpu/drm/i915/intel_gt_pm.h |   1 -
 5 files changed, 162 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5c10acf767a8..a57b20f95cdc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3406,7 +3406,6 @@ extern void i915_redisable_vga(struct drm_i915_private 
*dev_priv);
 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
-extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  bool enable);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f815da0dd991..d9cf4f81979e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1130,145 +1130,6 @@ static void notify_ring(struct intel_engine_cs *engine)
trace_intel_engine_notify(engine, wait);
 }
 
-static void vlv_c0_read(struct drm_i915_private *dev_priv,
-   struct intel_rps_ei *ei)
-{
-   ei->ktime = ktime_get_raw();
-   ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
-   ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
-}
-
-void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
-{
-   memset(_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
-}
-
-static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
-{
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   const struct intel_rps_ei *prev = >ei;
-   struct intel_rps_ei now;
-   u32 events = 0;
-
-   if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
-   return 0;
-
-   vlv_c0_read(dev_priv, );
-
-   if (prev->ktime) {
-   u64 time, c0;
-   u32 render, media;
-
-   time = ktime_us_delta(now.ktime, prev->ktime);
-
-   time *= dev_priv->czclk_freq;
-
-   /* Workload can be split between render + media,
-* e.g. SwapBuffers being blitted in X after being rendered in
-* mesa. To account for this we need to combine both engines
-* into our activity counter.
-*/
-   render = now.render_c0 - prev->render_c0;
-   media = now.media_c0 - prev->media_c0;
-   c0 = max(render, media);
-   c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
-
-   if (c0 > time * rps->up_threshold)
-   events = GEN6_PM_RP_UP_THRESHOLD;
-   else if (c0 < time * rps->down_threshold)
-   events = GEN6_PM_RP_DOWN_THRESHOLD;
-   }
-
-   rps->ei = now;
-   return events;
-}
-
-static void gen6_pm_rps_work(struct work_struct *work)
-{
-   struct drm_i915_private *dev_priv =
-   container_of(work, struct drm_i915_private, gt_pm.rps.work);
-   struct intel_rps *rps = _priv->gt_pm.rps;
-   bool client_boost = false;
-   int new_delay, adj, min, max;
-   u32 pm_iir = 0;
-
-   spin_lock_irq(_priv->irq_lock);
-   if (rps->interrupts_enabled) {
-   pm_iir = fetch_and_zero(>pm_iir);
-   client_boost = atomic_read(>num_waiters);
-   }
-   spin_unlock_irq(_priv->irq_lock);
-
-   /* Make sure we didn't queue anything we're not going to process. */
-   WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
-   if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
-   goto out;
-
-   mutex_lock(>lock);
-
-   pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
-
-   adj = rps->last_adj;
-   new_delay = rps->cur_freq;
-   min = rps->min_freq_softlimit;
-   max = rps->max_freq_softlimit;
-   if (client_boost)
-   max = rps->max_freq;
-   if (client_boost && new_delay < rps->boost_freq) {
-   new_delay = rps->boost_freq;
-   adj = 0;
-   } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
-   if (adj > 0)
-   adj *= 2;
-   else /* CHV needs even encode values */
-   adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
-
-   if (new_delay >= rps->max_freq_softlimit)
-   adj