Re: [Intel-gfx] [PATCH 3/3] drm/i915/psr: Enable PSR1 on gen-9+ HW
On Fri, 2018-09-07 at 08:35 -0700, Nathan Ciobanu wrote:
> On Thu, Sep 06, 2018 at 11:21:35PM -0700, Dhinakaran Pandiyan wrote:
> > We have new tests and fixes in place since the feature was last
> > disabled.
> >
> > Try again for gen-9+ hardware and enable only PSR1 as a first step.
>
> Since this patch explicitly disables PSR2 for all platforms maybe
> you
> can clarify that in the commit message or disable PSR2 in a separate
> patch. It will help with productized kernels ;)
It doesn't actually disable, since PSR2 was not enabled in the first
place. i915.enable_psr=1 will still enable PSR2 on a compatible panel.
i915.enable_psr=-1, the default option, will now enable PSR1.
Unless you are saying the patch is not doing what I'm claiming :)
> >
> > Cc: Jani Nikula
> > Cc: Jose Roberto de Souza
> > Cc: Paulo Zanoni
> > Cc: Rodrigo Vivi
> > Cc: Ville Syrjälä
> > References: 2ee7dc497e34 ("drm/i915: disable PSR by default on
> > HSW/BDW")
> > References: dcb2e993f3c0 ("Revert "drm/i915: Enable PSR by default
> > on Valleyview and Cherryview."")
> > Signed-off-by: Dhinakaran Pandiyan
> > ---
> > drivers/gpu/drm/i915/intel_psr.c | 17 -
> > 1 file changed, 8 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index b6838b525502..fc823f93a4dc 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
> > static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> >const struct intel_crtc_state
> > *crtc_state)
> > {
> > + /* Disable PSR2 by default for all platforms */
> > + if (i915_modparams.enable_psr == -1)
> > + return false;
> > +
> > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> > case I915_PSR_DEBUG_FORCE_PSR1:
> > return false;
> > @@ -1051,7 +1055,7 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > * intel_psr_init - Init basic PSR work and mutex.
> > * @dev_priv: i915 device private
> > *
> > - * This function is called only once at driver load to initialize
> > basic
> > + * This function is called only once at driver load to initialize
> > basic
> > * PSR stuff.
> > */
> > void intel_psr_init(struct drm_i915_private *dev_priv)
> > @@ -1065,19 +1069,14 @@ void intel_psr_init(struct drm_i915_private
> > *dev_priv)
> > if (!dev_priv->psr.sink_support)
> > return;
> >
> > - if (i915_modparams.enable_psr == -1) {
> > - i915_modparams.enable_psr = dev_priv-
> > >vbt.psr.enable;
> > -
> > - /* Per platform default: all disabled. */
> > - i915_modparams.enable_psr = 0;
> > - }
> > + if (i915_modparams.enable_psr == -1)
> > + if (INTEL_GEN(dev_priv) < 9 || !dev_priv-
> > >vbt.psr.enable)
> > + i915_modparams.enable_psr = 0;
> >
> > - /* Set link_standby x link_off defaults */
> > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> > /* HSW and BDW require workarounds that we don't
> > implement. */
> > dev_priv->psr.link_standby = false;
> > else
> > - /* For new platforms let's respect VBT back again
> > */
> > dev_priv->psr.link_standby = dev_priv-
> > >vbt.psr.full_link;
> >
> > INIT_WORK(_priv->psr.work, intel_psr_work);
> > --
> > 2.17.1
> >
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/psr: Enable PSR1 on gen-9+ HW
On Thu, Sep 06, 2018 at 11:21:35PM -0700, Dhinakaran Pandiyan wrote:
> We have new tests and fixes in place since the feature was last
> disabled.
>
> Try again for gen-9+ hardware and enable only PSR1 as a first step.
Since this patch explicitly disables PSR2 for all platforms maybe you
can clarify that in the commit message or disable PSR2 in a separate
patch. It will help with productized kernels ;)
>
> Cc: Jani Nikula
> Cc: Jose Roberto de Souza
> Cc: Paulo Zanoni
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> References: 2ee7dc497e34 ("drm/i915: disable PSR by default on HSW/BDW")
> References: dcb2e993f3c0 ("Revert "drm/i915: Enable PSR by default on
> Valleyview and Cherryview."")
> Signed-off-by: Dhinakaran Pandiyan
> ---
> drivers/gpu/drm/i915/intel_psr.c | 17 -
> 1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index b6838b525502..fc823f93a4dc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
> static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state)
> {
> + /* Disable PSR2 by default for all platforms */
> + if (i915_modparams.enable_psr == -1)
> + return false;
> +
> switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
> case I915_PSR_DEBUG_FORCE_PSR1:
> return false;
> @@ -1051,7 +1055,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> * intel_psr_init - Init basic PSR work and mutex.
> * @dev_priv: i915 device private
> *
> - * This function is called only once at driver load to initialize basic
> + * This function is called only once at driver load to initialize basic
> * PSR stuff.
> */
> void intel_psr_init(struct drm_i915_private *dev_priv)
> @@ -1065,19 +1069,14 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> if (!dev_priv->psr.sink_support)
> return;
>
> - if (i915_modparams.enable_psr == -1) {
> - i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
> -
> - /* Per platform default: all disabled. */
> - i915_modparams.enable_psr = 0;
> - }
> + if (i915_modparams.enable_psr == -1)
> + if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
> + i915_modparams.enable_psr = 0;
>
> - /* Set link_standby x link_off defaults */
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> else
> - /* For new platforms let's respect VBT back again */
> dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>
> INIT_WORK(_priv->psr.work, intel_psr_work);
> --
> 2.17.1
>
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[Intel-gfx] [PATCH 3/3] drm/i915/psr: Enable PSR1 on gen-9+ HW
We have new tests and fixes in place since the feature was last
disabled.
Try again for gen-9+ hardware and enable only PSR1 as a first step.
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Paulo Zanoni
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
References: 2ee7dc497e34 ("drm/i915: disable PSR by default on HSW/BDW")
References: dcb2e993f3c0 ("Revert "drm/i915: Enable PSR by default on
Valleyview and Cherryview."")
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_psr.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..fc823f93a4dc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
+ /* Disable PSR2 by default for all platforms */
+ if (i915_modparams.enable_psr == -1)
+ return false;
+
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
@@ -1051,7 +1055,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
* intel_psr_init - Init basic PSR work and mutex.
* @dev_priv: i915 device private
*
- * This function is called only once at driver load to initialize basic
+ * This function is called only once at driver load to initialize basic
* PSR stuff.
*/
void intel_psr_init(struct drm_i915_private *dev_priv)
@@ -1065,19 +1069,14 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (!dev_priv->psr.sink_support)
return;
- if (i915_modparams.enable_psr == -1) {
- i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
-
- /* Per platform default: all disabled. */
- i915_modparams.enable_psr = 0;
- }
+ if (i915_modparams.enable_psr == -1)
+ if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
+ i915_modparams.enable_psr = 0;
- /* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
dev_priv->psr.link_standby = false;
else
- /* For new platforms let's respect VBT back again */
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
INIT_WORK(_priv->psr.work, intel_psr_work);
--
2.17.1
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