On Fri, 14 Oct 2022, "Kahola, Mika" wrote:
> Maybe these could be moved into intel_cx0_reg_defs.h file?
Register definitions to intel_cx0_regs.h. See
$ find drivers/gpu/drm/i915/ -name "*_regs.h"
Any common helpers such as REG_FIELD_GET8() and friends to
i915_reg_defs.h where we already have
> -Original Message-
> From: Jani Nikula
> Sent: Friday, September 30, 2022 12:32 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Add support for C10 phy
> programming
>
> On Thu, 29 Sep 2022, Mika
On Thu, 29 Sep 2022, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> Add sequences for C10 phy enable/disable phy lane reset,
> powerdown change sequence and phy lane programming.
>
> Bspec: 64539, 67636, 65451, 65450, 64568
>
> Cc: Imre Deak
> Cc: Mika Kahola
> Cc: Uma Shankar
>
From: Radhakrishna Sripada
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 67636, 65451, 65450, 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
From: Radhakrishna Sripada
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 67636, 65451, 65450, 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
