Re: [Intel-gfx] [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable

2014-07-15 Thread Rodrigo Vivi 
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com


On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni przan...@gmail.com wrote:

 From: Paulo Zanoni paulo.r.zan...@intel.com

 Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
 so we can reuse the nice IRQ macros we have there. The main difference
 is that now we're going to check if the IIR register is non-zero when
 we try to re-enable the interrupts.

 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
 ---
  drivers/gpu/drm/i915/i915_irq.c  | 12 
  drivers/gpu/drm/i915/intel_drv.h |  1 +
  drivers/gpu/drm/i915/intel_pm.c  | 18 ++
  3 files changed, 15 insertions(+), 16 deletions(-)

 diff --git a/drivers/gpu/drm/i915/i915_irq.c
 b/drivers/gpu/drm/i915/i915_irq.c
 index 2e116e9d..a8b8b6b 100644
 --- a/drivers/gpu/drm/i915/i915_irq.c
 +++ b/drivers/gpu/drm/i915/i915_irq.c
 @@ -3204,6 +3204,18 @@ static void gen8_irq_reset(struct drm_device *dev)
 ibx_irq_reset(dev);
  }

 +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
 +{
 +   unsigned long irqflags;
 +
 +   spin_lock_irqsave(dev_priv-irq_lock, irqflags);
 +   GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv-de_irq_mask[PIPE_B],
 + ~dev_priv-de_irq_mask[PIPE_B]);
 +   GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv-de_irq_mask[PIPE_C],
 + ~dev_priv-de_irq_mask[PIPE_C]);
 +   spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
 +}
 +
  static void cherryview_irq_preinstall(struct drm_device *dev)
  {
 struct drm_i915_private *dev_priv = dev-dev_private;
 diff --git a/drivers/gpu/drm/i915/intel_drv.h
 b/drivers/gpu/drm/i915/intel_drv.h
 index 5f7c7bd..46a3a09 100644
 --- a/drivers/gpu/drm/i915/intel_drv.h
 +++ b/drivers/gpu/drm/i915/intel_drv.h
 @@ -687,6 +687,7 @@ void intel_runtime_pm_disable_interrupts(struct
 drm_device *dev);
  void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
  int intel_get_crtc_scanline(struct intel_crtc *crtc);
  void i9xx_check_fifo_underruns(struct drm_device *dev);
 +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);


  /* intel_crt.c */
 diff --git a/drivers/gpu/drm/i915/intel_pm.c
 b/drivers/gpu/drm/i915/intel_pm.c
 index 31ae2b4..4cc9e5c 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -5913,7 +5913,6 @@ bool intel_display_power_enabled(struct
 drm_i915_private *dev_priv,
  static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
  {
 struct drm_device *dev = dev_priv-dev;
 -   unsigned long irqflags;

 /*
  * After we re-enable the power well, if we touch VGA register
 0x3d5
 @@ -5929,21 +5928,8 @@ static void hsw_power_well_post_enable(struct
 drm_i915_private *dev_priv)
 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 vga_put(dev-pdev, VGA_RSRC_LEGACY_IO);

 -   if (IS_BROADWELL(dev)) {
 -   spin_lock_irqsave(dev_priv-irq_lock, irqflags);
 -   I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
 -  dev_priv-de_irq_mask[PIPE_B]);
 -   I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
 -  ~dev_priv-de_irq_mask[PIPE_B] |
 -  GEN8_PIPE_VBLANK);
 -   I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
 -  dev_priv-de_irq_mask[PIPE_C]);
 -   I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
 -  ~dev_priv-de_irq_mask[PIPE_C] |
 -  GEN8_PIPE_VBLANK);
 -   POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
 -   spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
 -   }
 +   if (IS_BROADWELL(dev))
 +   gen8_irq_power_well_post_enable(dev_priv);
  }

  static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 --
 2.0.0

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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[Intel-gfx] [PATCH 3/5] drm/i915: extract and improve gen8_irq_power_well_post_enable

2014-07-04 Thread Paulo Zanoni 
From: Paulo Zanoni paulo.r.zan...@intel.com

Move it from hsw_power_well_post_enable() (intel_pm.c) to i915_irq.c
so we can reuse the nice IRQ macros we have there. The main difference
is that now we're going to check if the IIR register is non-zero when
we try to re-enable the interrupts.

Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
 drivers/gpu/drm/i915/i915_irq.c  | 12 
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 18 ++
 3 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e116e9d..a8b8b6b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3204,6 +3204,18 @@ static void gen8_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev);
 }
 
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
+{
+   unsigned long irqflags;
+
+   spin_lock_irqsave(dev_priv-irq_lock, irqflags);
+   GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv-de_irq_mask[PIPE_B],
+ ~dev_priv-de_irq_mask[PIPE_B]);
+   GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv-de_irq_mask[PIPE_C],
+ ~dev_priv-de_irq_mask[PIPE_C]);
+   spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
+}
+
 static void cherryview_irq_preinstall(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev-dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5f7c7bd..46a3a09 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -687,6 +687,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_device 
*dev);
 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 void i9xx_check_fifo_underruns(struct drm_device *dev);
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
 
 
 /* intel_crt.c */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..4cc9e5c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5913,7 +5913,6 @@ bool intel_display_power_enabled(struct drm_i915_private 
*dev_priv,
 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 {
struct drm_device *dev = dev_priv-dev;
-   unsigned long irqflags;
 
/*
 * After we re-enable the power well, if we touch VGA register 0x3d5
@@ -5929,21 +5928,8 @@ static void hsw_power_well_post_enable(struct 
drm_i915_private *dev_priv)
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(dev-pdev, VGA_RSRC_LEGACY_IO);
 
-   if (IS_BROADWELL(dev)) {
-   spin_lock_irqsave(dev_priv-irq_lock, irqflags);
-   I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
-  dev_priv-de_irq_mask[PIPE_B]);
-   I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
-  ~dev_priv-de_irq_mask[PIPE_B] |
-  GEN8_PIPE_VBLANK);
-   I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
-  dev_priv-de_irq_mask[PIPE_C]);
-   I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
-  ~dev_priv-de_irq_mask[PIPE_C] |
-  GEN8_PIPE_VBLANK);
-   POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
-   spin_unlock_irqrestore(dev_priv-irq_lock, irqflags);
-   }
+   if (IS_BROADWELL(dev))
+   gen8_irq_power_well_post_enable(dev_priv);
 }
 
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
-- 
2.0.0

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