Re: [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote: > Create a separate file to store registers for PICA chips > C10 and C20. > > v2: Rename file (Jani) > v3: Use _PICK_EVEN_2RANGES() macro (Lucas) > Coding style fixed (Lucas) > > Signed-off-by: Radhakrishna Sripada > Signed-off-by: Mika Kahola > --- You might need to adjust some tabs before pushing I feel.. Reviewed-by: Vinod Govindapillai > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131 ++ > 1 file changed, 131 insertions(+) > create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > new file mode 100644 > index ..d1ee8a2fc9cf > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -0,0 +1,131 @@ > +/* SPDX-License-Identifier: MIT > + * > + * Copyright © 2022 Intel Corporation > + */ > + > +#ifndef __INTEL_CX0_PHY_REGS_H__ > +#define __INTEL_CX0_PHY_REGS_H__ > + > +#include "i915_reg_defs.h" > + > +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 > +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 > +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 > +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 > +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) > _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) > +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) > +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASKREG_GENMASK(30, 27) > +#define > XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED > REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, > 0x1) > +#define > XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED > REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, > 0x2) > +#define > XELPDP_PORT_M2P_COMMAND_READ > REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, > 0x3) > +#define XELPDP_PORT_M2P_DATA_MASKREG_GENMASK(23, 16) > +#define XELPDP_PORT_M2P_DATA(val) > REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, > val) > +#define XELPDP_PORT_M2P_TRANSACTION_RESETREG_BIT(15) > +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) > +#define > XELPDP_PORT_M2P_ADDRESS(val) > REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) > +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) > _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ > + > > _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) > +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) > +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASKREG_GENMASK(30, 27) > +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 > +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK0x5 > +#define XELPDP_PORT_P2M_DATA_MASKREG_GENMASK(23, 16) > +#define XELPDP_PORT_P2M_DATA(val) > REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, > val) > +#define XELPDP_PORT_P2M_ERROR_SETREG_BIT(15) > + > +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1 > +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 > +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 > +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 > +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 > +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 > +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US100 > +#define XELPDP_PORT_RESET_END_TIMEOUT 15 > +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US1 > + > +#define _XELPDP_PORT_BUF_CTL1_LN0_A0x64004 > +#define _XELPDP_PORT_BUF_CTL1_LN0_B0x64104 > +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC10x16F200 > +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC20x16F400 > +#define XELPDP_PORT_BUF_CTL1(port) >
[Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers
Create a separate file to store registers for PICA chips C10 and C20. v2: Rename file (Jani) v3: Use _PICK_EVEN_2RANGES() macro (Lucas) Coding style fixed (Lucas) Signed-off-by: Radhakrishna Sripada Signed-off-by: Mika Kahola --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131 ++ 1 file changed, 131 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h new file mode 100644 index ..d1ee8a2fc9cf --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_CX0_PHY_REGS_H__ +#define __INTEL_CX0_PHY_REGS_H__ + +#include "i915_reg_defs.h" + +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) +#define XELPDP_PORT_M2P_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) +#define XELPDP_PORT_M2P_TRANSACTION_RESETREG_BIT(15) +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASKREG_GENMASK(30, 27) +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK0x5 +#define XELPDP_PORT_P2M_DATA_MASKREG_GENMASK(23, 16) +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) +#define XELPDP_PORT_P2M_ERROR_SETREG_BIT(15) + +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1 +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US100 +#define XELPDP_PORT_RESET_END_TIMEOUT 15 +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US1 + +#define _XELPDP_PORT_BUF_CTL1_LN0_A0x64004 +#define _XELPDP_PORT_BUF_CTL1_LN0_B0x64104 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC10x16F200 +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC20x16F400 +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ + _XELPDP_PORT_BUF_CTL1_LN0_A, \ + _XELPDP_PORT_BUF_CTL1_LN0_B, \ + _XELPDP_PORT_BUF_CTL1_LN0_USBC1,
