Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add definitions for MI_MATH command

[Chris Wilson]

Quoting Michał Winiarski (2019-09-26 11:06:33)
> We can use it in i915 for updating parts of unmasked registers from
> within a batch. We're also adding Gen8+ versions of CS_GPR registers
> (aka MI_MATH_REG in the coprocessor).
> 
> Signed-off-by: Michał Winiarski 
> Cc: Chris Wilson 

Checked against mesa's xml for convenience,
Reviewed-by: Chris Wilson 

> ---
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 
>  drivers/gpu/drm/i915/i915_reg.h  |  4 
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 9211b1ad401b..26c286bc9625 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -241,6 +241,30 @@
>  #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH   (1<<0)
>  #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>  
> +#define MI_MATH(x) MI_INSTR(0x1A, (x)-1)
> +#define MI_MATH_INSTR(opcode, op1, op2) (((opcode) << 20) | \
> +((op1) << 10) | (op2))

Perhaps this would benefit from a touch of REG_FIELD for value checking.
-Chris
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[Intel-gfx] [PATCH 4/6] drm/i915: Add definitions for MI_MATH command

[Michał Winiarski]

We can use it in i915 for updating parts of unmasked registers from
within a batch. We're also adding Gen8+ versions of CS_GPR registers
(aka MI_MATH_REG in the coprocessor).

Signed-off-by: Michał Winiarski 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 
 drivers/gpu/drm/i915/i915_reg.h  |  4 
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 9211b1ad401b..26c286bc9625 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -241,6 +241,30 @@
 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH   (1<<0)
 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
 
+#define MI_MATH(x) MI_INSTR(0x1A, (x)-1)
+#define MI_MATH_INSTR(opcode, op1, op2) (((opcode) << 20) | \
+((op1) << 10) | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define   MI_MATH_NOOP MI_MATH_INSTR(0x0, 0x0, 0x0)
+#define   MI_MATH_LOAD(op1, op2)   MI_MATH_INSTR(0x80, op1, op2)
+#define   MI_MATH_LOADINV(op1, op2)MI_MATH_INSTR(0x480, op1, op2)
+#define   MI_MATH_LOAD0(op1)   MI_MATH_INSTR(0x081, op1)
+#define   MI_MATH_LOAD1(op1)   MI_MATH_INSTR(0x481, op1)
+#define   MI_MATH_ADD  MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define   MI_MATH_SUB  MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define   MI_MATH_AND  MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define   MI_MATH_OR   MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define   MI_MATH_XOR  MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define   MI_MATH_STORE(op1, op2)  MI_MATH_INSTR(0x180, op1, op2)
+#define   MI_MATH_STOREINV(op1, op2)   MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define   MI_MATH_REG(x)   (x)
+#define   MI_MATH_REG_SRCA 0x20
+#define   MI_MATH_REG_SRCB 0x21
+#define   MI_MATH_REG_ACCU 0x31
+#define   MI_MATH_REG_ZF   0x32
+#define   MI_MATH_REG_CF   0x33
+
 /*
  * Commands used only by the command parser
  */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..fbedf89fc0bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2483,6 +2483,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   RING_WAIT(1 << 11) /* gen3+, PRBx_CTL */
 #define   RING_WAIT_SEMAPHORE  (1 << 10) /* gen6+ */
 
+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
+#define GEN8_RING_CS_GPR(base, n)  _MMIO(((base) + 0x600) + (n) * 8)
+#define GEN8_RING_CS_GPR_UDW(base, n)  _MMIO(((base) + 0x600) + (n) * 8 + 4)
+
 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW  (0 << 28)/* CFL+ & Gen11+ */
 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD  (1 << 28)
-- 
2.21.0

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