On Tue, Apr 04, 2023 at 10:22:53PM +0300, Sripada, Radhakrishna wrote:
>
>
> > -Original Message-
> > From: Deak, Imre
> > Sent: Tuesday, April 4, 2023 11:03 AM
> > To: Sripada, Radhakrishna
> > Cc: Kahola, Mika ; intel-gfx@lists.freedesktop.org;
> > Shankar, Uma ; Sousa, Gustavo
> >
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, April 4, 2023 11:03 AM
> To: Sripada, Radhakrishna
> Cc: Kahola, Mika ; intel-gfx@lists.freedesktop.org;
> Shankar, Uma ; Sousa, Gustavo
>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
On Tue, Apr 04, 2023 at 07:50:00PM +0300, Sripada, Radhakrishna wrote:
>
>
> > -Original Message-
> > From: Deak, Imre
> > Sent: Tuesday, April 4, 2023 6:28 AM
> > To: Kahola, Mika
> > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > ; Shankar, Uma ;
> > Sousa, Gustavo
>
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, April 4, 2023 6:28 AM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> ; Shankar, Uma ;
> Sousa, Gustavo
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> [...]
> > >
> > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > > > > +struct intel_c10mpllb_state
> > > > > +*pll_state) {
> > > > > + struct drm_i915_private *i915 =
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, April 4, 2023 2:47 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> ; Shankar, Uma ;
> Sousa, Gustavo
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
On Tue, Apr 04, 2023 at 01:43:20PM +0300, Kahola, Mika wrote:
> [...]
> > > +static int __intel_cx0_read(struct drm_i915_private *i915, enum port
> > > port,
> > > + int lane, u16 addr, u32 *val)
> > > +{
> > > + enum phy phy = intel_port_to_phy(i915, port);
> > > + int
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, March 29, 2023 6:41 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> ; Shankar, Uma ;
> Sousa, Gustavo
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
> -Original Message-
> From: Deak, Imre
> Sent: Monday, April 3, 2023 1:36 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> ; Shankar, Uma ;
> Sousa, Gustavo
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
On Mon, Apr 03, 2023 at 01:19:48PM +0300, Kahola, Mika wrote:
> > -Original Message-
> > From: Deak, Imre
> > Sent: Monday, April 3, 2023 1:12 PM
> > To: Kahola, Mika
> > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > ; Shankar, Uma ;
> > Sousa, Gustavo
> > Subject: Re:
> -Original Message-
> From: Deak, Imre
> Sent: Monday, April 3, 2023 1:12 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> ; Shankar, Uma ;
> Sousa, Gustavo
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll
On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
>
On Wed, Mar 29, 2023 at 06:40:39PM +0300, Imre Deak wrote:
> On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> [...]
> > +}
> > +
> > +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port
> > port, int lane, u32 *val)
> > +{
> > + enum phy phy =
On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
>
Hi Mika
There were some comments from the previous version
https://patchwork.freedesktop.org/patch/517048/#comment_943150
I think you should address them?
BR
vinod
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from
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