Re: [Intel-gfx] [PATCH 4/7] drm/i915: Use down ei for manual Baytrail RPS calculations
On Friday 06 March 2015 08:36 PM, Chris Wilson wrote:
Use both up/down manual ei calcuations for symmetry and greater
flexibility for reclocking, instead of faking the down interrupt based
on a fixed integer number of up interrupts.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_irq.c | 15 ++-
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 5 ++---
4 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 73292a183492..efa98c9e5777 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1028,8 +1028,6 @@ struct intel_gen6_power_mgmt {
u8 rp0_freq;/* Non-overclocked max frequency. */
u32 cz_freq;
- u32 ei_interrupt_count;
-
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b7b86298b37..8892dbdfb629 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1033,7 +1033,6 @@ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
{
vlv_c0_read(dev_priv, dev_priv-rps.down_ei);
dev_priv-rps.up_ei = dev_priv-rps.down_ei;
- dev_priv-rps.ei_interrupt_count = 0;
}
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
@@ -1041,23 +1040,13 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private
*dev_priv, u32 pm_iir)
struct intel_rps_ei now;
u32 events = 0;
- if ((pm_iir GEN6_PM_RP_UP_EI_EXPIRED) == 0)
+ if ((pm_iir (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
== 0)
return 0;
vlv_c0_read(dev_priv, now);
if (now.cz_clock == 0)
return 0;
- /*
-* To down throttle, C0 residency should be less than down threshold
-* for continous EI intervals. So calculate down EI counters
-* once in VLV_INT_COUNT_FOR_DOWN_EI
-*/
- if (++dev_priv-rps.ei_interrupt_count = VLV_INT_COUNT_FOR_DOWN_EI) {
- pm_iir |= GEN6_PM_RP_DOWN_EI_EXPIRED;
- dev_priv-rps.ei_interrupt_count = 0;
- }
-
if (pm_iir GEN6_PM_RP_DOWN_EI_EXPIRED) {
if (!vlv_c0_above(dev_priv,
dev_priv-rps.down_ei, now,
@@ -4247,7 +4236,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv) !IS_CHERRYVIEW(dev_priv))
/* WaGsvRC0ResidencyMethod:vlv */
- dev_priv-pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+ dev_priv-pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED;
else
dev_priv-pm_rps_events = GEN6_PM_RPS_EVENTS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 324922d8f8a1..ca24a2d4a823 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -665,7 +665,6 @@ enum skl_disp_power_wells {
#define VLV_CZ_CLOCK_TO_MILLI_SEC 10
#define VLV_RP_UP_EI_THRESHOLD90
#define VLV_RP_DOWN_EI_THRESHOLD 70
-#define VLV_INT_COUNT_FOR_DOWN_EI 5
/* vlv2 north clock has */
#define CCK_FUSE_REG 0x8
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b37d634bea99..55dc406cd195 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3784,11 +3784,10 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
u32 mask = 0;
if (val dev_priv-rps.min_freq_softlimit)
- mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
+ mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT;
if (val dev_priv-rps.max_freq_softlimit)
- mask |= GEN6_PM_RP_UP_THRESHOLD;
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
- mask |= dev_priv-pm_rps_events (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
mask = dev_priv-pm_rps_events;
return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
Patch looks fine
Reviewed-by: Deepak Sdeepa...@linux.intel.com
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[Intel-gfx] [PATCH 4/7] drm/i915: Use down ei for manual Baytrail RPS calculations
Use both up/down manual ei calcuations for symmetry and greater
flexibility for reclocking, instead of faking the down interrupt based
on a fixed integer number of up interrupts.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_irq.c | 15 ++-
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 5 ++---
4 files changed, 4 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 73292a183492..efa98c9e5777 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1028,8 +1028,6 @@ struct intel_gen6_power_mgmt {
u8 rp0_freq;/* Non-overclocked max frequency. */
u32 cz_freq;
- u32 ei_interrupt_count;
-
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b7b86298b37..8892dbdfb629 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1033,7 +1033,6 @@ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
{
vlv_c0_read(dev_priv, dev_priv-rps.down_ei);
dev_priv-rps.up_ei = dev_priv-rps.down_ei;
- dev_priv-rps.ei_interrupt_count = 0;
}
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
@@ -1041,23 +1040,13 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private
*dev_priv, u32 pm_iir)
struct intel_rps_ei now;
u32 events = 0;
- if ((pm_iir GEN6_PM_RP_UP_EI_EXPIRED) == 0)
+ if ((pm_iir (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
== 0)
return 0;
vlv_c0_read(dev_priv, now);
if (now.cz_clock == 0)
return 0;
- /*
-* To down throttle, C0 residency should be less than down threshold
-* for continous EI intervals. So calculate down EI counters
-* once in VLV_INT_COUNT_FOR_DOWN_EI
-*/
- if (++dev_priv-rps.ei_interrupt_count = VLV_INT_COUNT_FOR_DOWN_EI) {
- pm_iir |= GEN6_PM_RP_DOWN_EI_EXPIRED;
- dev_priv-rps.ei_interrupt_count = 0;
- }
-
if (pm_iir GEN6_PM_RP_DOWN_EI_EXPIRED) {
if (!vlv_c0_above(dev_priv,
dev_priv-rps.down_ei, now,
@@ -4247,7 +4236,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv) !IS_CHERRYVIEW(dev_priv))
/* WaGsvRC0ResidencyMethod:vlv */
- dev_priv-pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
+ dev_priv-pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED;
else
dev_priv-pm_rps_events = GEN6_PM_RPS_EVENTS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 324922d8f8a1..ca24a2d4a823 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -665,7 +665,6 @@ enum skl_disp_power_wells {
#define VLV_CZ_CLOCK_TO_MILLI_SEC 10
#define VLV_RP_UP_EI_THRESHOLD 90
#define VLV_RP_DOWN_EI_THRESHOLD 70
-#define VLV_INT_COUNT_FOR_DOWN_EI 5
/* vlv2 north clock has */
#define CCK_FUSE_REG 0x8
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b37d634bea99..55dc406cd195 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3784,11 +3784,10 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private
*dev_priv, u8 val)
u32 mask = 0;
if (val dev_priv-rps.min_freq_softlimit)
- mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
+ mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT;
if (val dev_priv-rps.max_freq_softlimit)
- mask |= GEN6_PM_RP_UP_THRESHOLD;
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
- mask |= dev_priv-pm_rps_events (GEN6_PM_RP_DOWN_EI_EXPIRED |
GEN6_PM_RP_UP_EI_EXPIRED);
mask = dev_priv-pm_rps_events;
return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
--
2.1.4
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