Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-21 Thread Yang, Libin 

> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, October 20, 2016 8:03 PM
> To: Nikula, Jani <jani.nik...@intel.com>
> Cc: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org; Zhang, Keqiao
> <keqiao.zh...@intel.com>; libin.y...@linux.intel.com; Pandiyan,
> Dhinakaran <dhinakaran.pandi...@intel.com>; Zhao, Juan J
> <juan.j.z...@intel.com>
> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> On Thu, Oct 20, 2016 at 02:34:34PM +0300, Jani Nikula wrote:
> > On Thu, 20 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
> > >> >> Any particular reason these M/N values are half of what they're
> > >> >> in table
> > >> >> 2-104 of DP 1.4 spec? (Admittedly the table is an informative
> > >> >> example.)
> > >> >
> > >> > For HDMI, we found only set N is enough. HW then can handle the
> > >> remaining.
> > >>
> > >> I meant, the M and N values in this part of the dp_aud_n_m table
> > >> are 1/2 of what they are in the DP spec table. Why?
> > >
> > > Which table are you meaning? I calculate the values myself. I didn't
> > > find the full table in DP spec. I only find the table for 270MHz and
> > > 162MHz in Table 2-50: Examples of Maud and Naud Values
> >
> > Table 2-104 in DP 1.4. Maybe you're looking at an older version of the
> > spec.
> 
> So it looks like they used the same M value for all link frequencies in that
> example, which for 540M ends up being double what the minimal accurate
> value is. But as both M and N are doubled the ratio is still exactly the same.

There is a formula in DP 1.2 spec:
Maud/Naud = 512 * fs / f_LS_Clk

Suppose all the values meeting the formula is acceptable.

> 
> And there is indeed a 64k and 128k bitrates added as well. Those are not
> classified under HBR audio. But as those can't be expressed via short audio
> descriptors in the EDID, I don't think they would be accepted by ALSA. Or am
> I wrong? I do wonder how they are supposed to be used though since there
> must be some way for the sink to advertise them, otherwise I can't see the
> point in adding them.

Oh, sorry, I was thinking 128k is HBR. I didn't see 64k and 128k description
in DP 1.2 spec. 

Regards,
Libin

> 
> --
> Ville Syrjälä
> Intel OTC
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Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-21 Thread Yang, Libin 
Hi Jani,

> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, October 20, 2016 7:35 PM
> To: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> <dhinakaran.pandi...@intel.com>; Zhang, Keqiao
> <keqiao.zh...@intel.com>; Zhao, Juan J <juan.j.z...@intel.com>
> Subject: RE: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> On Thu, 20 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
> >> >> Any particular reason these M/N values are half of what they're in
> >> >> table
> >> >> 2-104 of DP 1.4 spec? (Admittedly the table is an informative
> >> >> example.)
> >> >
> >> > For HDMI, we found only set N is enough. HW then can handle the
> >> remaining.
> >>
> >> I meant, the M and N values in this part of the dp_aud_n_m table are
> >> 1/2 of what they are in the DP spec table. Why?
> >
> > Which table are you meaning? I calculate the values myself. I didn't
> > find the full table in DP spec. I only find the table for 270MHz and
> > 162MHz in Table 2-50: Examples of Maud and Naud Values
> 
> Table 2-104 in DP 1.4. Maybe you're looking at an older version of the spec.

I was referring DP1.2. I don't have DP 1.4 spec on hand. But suppose
both table should be OK?

Regards,
Libin

> 
> BR,
> Jani.
> 
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-20 Thread Ville Syrjälä 
On Thu, Oct 20, 2016 at 02:34:34PM +0300, Jani Nikula wrote:
> On Thu, 20 Oct 2016, "Yang, Libin"  wrote:
> >> >> Any particular reason these M/N values are half of what they're in
> >> >> table
> >> >> 2-104 of DP 1.4 spec? (Admittedly the table is an informative
> >> >> example.)
> >> >
> >> > For HDMI, we found only set N is enough. HW then can handle the
> >> remaining.
> >> 
> >> I meant, the M and N values in this part of the dp_aud_n_m table are 1/2 of
> >> what they are in the DP spec table. Why?
> >
> > Which table are you meaning? I calculate the values myself. I didn't find 
> > the
> > full table in DP spec. I only find the table for 270MHz and 162MHz in 
> > Table 2-50: Examples of Maud and Naud Values
> 
> Table 2-104 in DP 1.4. Maybe you're looking at an older version of the
> spec.

So it looks like they used the same M value for all link frequencies
in that example, which for 540M ends up being double what the minimal
accurate value is. But as both M and N are doubled the ratio is still
exactly the same.

And there is indeed a 64k and 128k bitrates added as well. Those are
not classified under HBR audio. But as those can't be expressed via
short audio descriptors in the EDID, I don't think they would be
accepted by ALSA. Or am I wrong? I do wonder how they are supposed to be
used though since there must be some way for the sink to advertise
them, otherwise I can't see the point in adding them.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-20 Thread Jani Nikula 
On Thu, 20 Oct 2016, "Yang, Libin"  wrote:
>> >> Any particular reason these M/N values are half of what they're in
>> >> table
>> >> 2-104 of DP 1.4 spec? (Admittedly the table is an informative
>> >> example.)
>> >
>> > For HDMI, we found only set N is enough. HW then can handle the
>> remaining.
>> 
>> I meant, the M and N values in this part of the dp_aud_n_m table are 1/2 of
>> what they are in the DP spec table. Why?
>
> Which table are you meaning? I calculate the values myself. I didn't find the
> full table in DP spec. I only find the table for 270MHz and 162MHz in 
> Table 2-50: Examples of Maud and Naud Values

Table 2-104 in DP 1.4. Maybe you're looking at an older version of the
spec.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-20 Thread Yang, Libin 

> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, October 20, 2016 4:34 PM
> To: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> <dhinakaran.pandi...@intel.com>; Zhang, Keqiao
> <keqiao.zh...@intel.com>; Zhao, Juan J <juan.j.z...@intel.com>
> Subject: RE: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> On Thu, 20 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
> >> -Original Message-
> >> From: Nikula, Jani
> >> Sent: Wednesday, October 19, 2016 11:09 PM
> >> To: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
> >> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org
> >> Cc: libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> >> <dhinakaran.pandi...@intel.com>; Zhang, Keqiao
> >> <keqiao.zh...@intel.com>; Zhao, Juan J <juan.j.z...@intel.com>
> >> Subject: RE: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M
> >> in modeset
> >>
> >>
> >> Sorry it's taken me forever to get back to this. Some comments inline.
> >>
> >> BR,
> >> Jani.
> >>
> >> On Wed, 12 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
> >> >> -Original Message-
> >> >> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org]
> >> >> On Behalf Of Lin, Mengdong
> >> >> Sent: Wednesday, October 12, 2016 10:46 AM
> >> >> To: Nikula, Jani <jani.nik...@intel.com>;
> >> >> intel-gfx@lists.freedesktop.org
> >> >> Cc: Nikula, Jani <jani.nik...@intel.com>;
> >> >> libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> >> >> <dhinakaran.pandi...@intel.com>
> >> >> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper
> >> >> N/M in modeset
> >> >>
> >> >>
> >> >>
> >> >> > -Original Message-
> >> >> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org]
> >> >> > On Behalf Of Jani Nikula
> >> >> > Sent: Monday, October 10, 2016 11:04 PM
> >> >> > To: intel-gfx@lists.freedesktop.org
> >> >> > Cc: Nikula, Jani <jani.nik...@intel.com>;
> >> >> > libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> >> >> > <dhinakaran.pandi...@intel.com>
> >> >> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M
> >> >> > in modeset
> >> >> >
> >> >> > When modeset occurs and the LS_CLK is set to some special values
> >> >> > in DP mode, the N/M need to be set manually if audio is playing.
> >> >> > Otherwise the first several seconds may be silent in audio playback.
> >> >> >
> >> >> > The relationship of Maud and Naud is expressed in the following
> >> equation:
> >> >> > Maud/Naud = 512 * fs / f_LS_Clk
> >> >> >
> >> >> > Please refer VESA DisplayPort Standard spec for details.
> >> >> >
> >> >> > Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
> >> >> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> >> >> > ---
> >> >> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
> >> >> >  drivers/gpu/drm/i915/intel_audio.c | 100
> >> >> > -
> >> >> >  2 files changed, 105 insertions(+), 2 deletions(-)
> >> >> >
> >> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> >> > b/drivers/gpu/drm/i915/i915_reg.h index
> >> >> > 595d196f753f..8d9dbc7d5b32
> >> >> > 100644
> >> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> >> > @@ -7359,6 +7359,13 @@ enum {
> >> >> >  #define _HSW_AUD_MISC_CTRL_B 0x65110
> >> >> >  #define HSW_AUD_MISC_CTRL(pipe)  _MMIO_PIPE(pipe,
> >> >> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> >> >> >
> >> >> > +#define _HSW_AUD_M_CTS_ENABLE_A  0x65028
> >> >> > +#define _HSW_AUD_M_CTS_ENABLE_B

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-20 Thread Jani Nikula 
On Thu, 20 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Wednesday, October 19, 2016 11:09 PM
>> To: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
>> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: libin.y...@linux.intel.com; Pandiyan, Dhinakaran
>> <dhinakaran.pandi...@intel.com>; Zhang, Keqiao
>> <keqiao.zh...@intel.com>; Zhao, Juan J <juan.j.z...@intel.com>
>> Subject: RE: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
>> modeset
>> 
>> 
>> Sorry it's taken me forever to get back to this. Some comments inline.
>> 
>> BR,
>> Jani.
>> 
>> On Wed, 12 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
>> >> -Original Message-
>> >> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> >> Behalf Of Lin, Mengdong
>> >> Sent: Wednesday, October 12, 2016 10:46 AM
>> >> To: Nikula, Jani <jani.nik...@intel.com>;
>> >> intel-gfx@lists.freedesktop.org
>> >> Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
>> >> Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
>> >> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M
>> >> in modeset
>> >>
>> >>
>> >>
>> >> > -Original Message-
>> >> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> >> > Behalf Of Jani Nikula
>> >> > Sent: Monday, October 10, 2016 11:04 PM
>> >> > To: intel-gfx@lists.freedesktop.org
>> >> > Cc: Nikula, Jani <jani.nik...@intel.com>;
>> >> > libin.y...@linux.intel.com; Pandiyan, Dhinakaran
>> >> > <dhinakaran.pandi...@intel.com>
>> >> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
>> >> > modeset
>> >> >
>> >> > When modeset occurs and the LS_CLK is set to some special values in
>> >> > DP mode, the N/M need to be set manually if audio is playing.
>> >> > Otherwise the first several seconds may be silent in audio playback.
>> >> >
>> >> > The relationship of Maud and Naud is expressed in the following
>> equation:
>> >> > Maud/Naud = 512 * fs / f_LS_Clk
>> >> >
>> >> > Please refer VESA DisplayPort Standard spec for details.
>> >> >
>> >> > Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
>> >> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>> >> > ---
>> >> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
>> >> >  drivers/gpu/drm/i915/intel_audio.c | 100
>> >> > -
>> >> >  2 files changed, 105 insertions(+), 2 deletions(-)
>> >> >
>> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >> > b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
>> >> > 100644
>> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> >> > @@ -7359,6 +7359,13 @@ enum {
>> >> >  #define _HSW_AUD_MISC_CTRL_B   0x65110
>> >> >  #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
>> >> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
>> >> >
>> >> > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
>> >> > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
>> >> > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
>> >> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
>> >> > +#define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
>> >> > +#define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
>> >> > +#define   AUD_CONFIG_M_MASK0xf
>> >>
>> >> The last line cause misalignment after applying the patch.
>> >>
>> >> > +
>> >> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
>> >> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
>> >> >  #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe,
>> >> > _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
>> diff --
>> >> git
>> >> > a/drivers/gpu/drm/i915/intel_audio.c
>> >&g

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-19 Thread Yang, Libin 

> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, October 19, 2016 11:09 PM
> To: Yang, Libin <libin.y...@intel.com>; Lin, Mengdong
> <mengdong@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> <dhinakaran.pandi...@intel.com>; Zhang, Keqiao
> <keqiao.zh...@intel.com>; Zhao, Juan J <juan.j.z...@intel.com>
> Subject: RE: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> 
> Sorry it's taken me forever to get back to this. Some comments inline.
> 
> BR,
> Jani.
> 
> On Wed, 12 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
> >> -Original Message-
> >> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> >> Behalf Of Lin, Mengdong
> >> Sent: Wednesday, October 12, 2016 10:46 AM
> >> To: Nikula, Jani <jani.nik...@intel.com>;
> >> intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
> >> Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
> >> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M
> >> in modeset
> >>
> >>
> >>
> >> > -Original Message-
> >> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> >> > Behalf Of Jani Nikula
> >> > Sent: Monday, October 10, 2016 11:04 PM
> >> > To: intel-gfx@lists.freedesktop.org
> >> > Cc: Nikula, Jani <jani.nik...@intel.com>;
> >> > libin.y...@linux.intel.com; Pandiyan, Dhinakaran
> >> > <dhinakaran.pandi...@intel.com>
> >> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> >> > modeset
> >> >
> >> > When modeset occurs and the LS_CLK is set to some special values in
> >> > DP mode, the N/M need to be set manually if audio is playing.
> >> > Otherwise the first several seconds may be silent in audio playback.
> >> >
> >> > The relationship of Maud and Naud is expressed in the following
> equation:
> >> > Maud/Naud = 512 * fs / f_LS_Clk
> >> >
> >> > Please refer VESA DisplayPort Standard spec for details.
> >> >
> >> > Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
> >> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
> >> >  drivers/gpu/drm/i915/intel_audio.c | 100
> >> > -
> >> >  2 files changed, 105 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> > b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
> >> > 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -7359,6 +7359,13 @@ enum {
> >> >  #define _HSW_AUD_MISC_CTRL_B0x65110
> >> >  #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe,
> >> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> >> >
> >> > +#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
> >> > +#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
> >> > +#define HSW_AUD_M_CTS_ENABLE(pipe)  _MMIO_PIPE(pipe,
> >> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> >> > +#define   AUD_M_CTS_M_VALUE_INDEX   (1 << 21)
> >> > +#define   AUD_M_CTS_M_PROG_ENABLE   (1 << 20)
> >> > +#define   AUD_CONFIG_M_MASK 0xf
> >>
> >> The last line cause misalignment after applying the patch.
> >>
> >> > +
> >> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_A  0x650b4
> >> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_B  0x651b4
> >> >  #define HSW_AUD_DIP_ELD_CTRL(pipe)  _MMIO_PIPE(pipe,
> >> > _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
> diff --
> >> git
> >> > a/drivers/gpu/drm/i915/intel_audio.c
> >> > b/drivers/gpu/drm/i915/intel_audio.c
> >> > index 81df29ca4947..0bc2701b6c9c 100644
> >> > --- a/drivers/gpu/drm/i915/intel_audio.c
> >> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> >> > @@ -57,6 +57,70 @@
> >> >   * struct _audio_component_audio_ops @audio_ops is called
> >> > from
> >> > i915 driver.
> >> >   */
> >> >
&g

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-19 Thread Jani Nikula 

Sorry it's taken me forever to get back to this. Some comments inline.

BR,
Jani.

On Wed, 12 Oct 2016, "Yang, Libin" <libin.y...@intel.com> wrote:
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>> Lin, Mengdong
>> Sent: Wednesday, October 12, 2016 10:46 AM
>> To: Nikula, Jani <jani.nik...@intel.com>; intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
>> Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
>> modeset
>> 
>> 
>> 
>> > -Original Message-
>> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
>> > Behalf Of Jani Nikula
>> > Sent: Monday, October 10, 2016 11:04 PM
>> > To: intel-gfx@lists.freedesktop.org
>> > Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
>> > Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
>> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
>> > modeset
>> >
>> > When modeset occurs and the LS_CLK is set to some special values in DP
>> > mode, the N/M need to be set manually if audio is playing. Otherwise
>> > the first several seconds may be silent in audio playback.
>> >
>> > The relationship of Maud and Naud is expressed in the following equation:
>> > Maud/Naud = 512 * fs / f_LS_Clk
>> >
>> > Please refer VESA DisplayPort Standard spec for details.
>> >
>> > Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
>> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
>> >  drivers/gpu/drm/i915/intel_audio.c | 100
>> > -
>> >  2 files changed, 105 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -7359,6 +7359,13 @@ enum {
>> >  #define _HSW_AUD_MISC_CTRL_B  0x65110
>> >  #define HSW_AUD_MISC_CTRL(pipe)   _MMIO_PIPE(pipe,
>> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
>> >
>> > +#define _HSW_AUD_M_CTS_ENABLE_A   0x65028
>> > +#define _HSW_AUD_M_CTS_ENABLE_B   0x65128
>> > +#define HSW_AUD_M_CTS_ENABLE(pipe)_MMIO_PIPE(pipe,
>> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
>> > +#define   AUD_M_CTS_M_VALUE_INDEX (1 << 21)
>> > +#define   AUD_M_CTS_M_PROG_ENABLE (1 << 20)
>> > +#define   AUD_CONFIG_M_MASK   0xf
>> 
>> The last line cause misalignment after applying the patch.
>> 
>> > +
>> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_A0x650b4
>> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_B0x651b4
>> >  #define HSW_AUD_DIP_ELD_CTRL(pipe)_MMIO_PIPE(pipe,
>> > _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) diff --
>> git
>> > a/drivers/gpu/drm/i915/intel_audio.c
>> > b/drivers/gpu/drm/i915/intel_audio.c
>> > index 81df29ca4947..0bc2701b6c9c 100644
>> > --- a/drivers/gpu/drm/i915/intel_audio.c
>> > +++ b/drivers/gpu/drm/i915/intel_audio.c
>> > @@ -57,6 +57,70 @@
>> >   * struct _audio_component_audio_ops @audio_ops is called from
>> > i915 driver.
>> >   */
>> >
>> > +/* DP N/M table */
>> > +#define LC_540M 54
>> > +#define LC_270M 27
>> > +#define LC_162M 162000
>> > +
>> > +struct dp_aud_n_m {
>> > +  int sample_rate;
>> > +  int clock;
>> > +  u16 n;
>> > +  u16 m;
>> > +};
>> > +
>> > +static const struct dp_aud_n_m dp_aud_n_m[] = {
>> > +  { 192000, LC_540M, 5625, 1024 },
>> > +  { 176400, LC_540M, 9375, 1568 },
>> > +  { 96000, LC_540M, 5625, 512 },
>> > +  { 88200, LC_540M, 9375, 784 },
>> > +  { 48000, LC_540M, 5625, 256 },
>> > +  { 44100, LC_540M, 9375, 392 },
>> > +  { 32000, LC_540M, 16875, 512 },

Any particular reason these M/N values are half of what they're in table
2-104 of DP 1.4 spec? (Admittedly the table is an informative example.)

>> > +  { 192000, LC_270M, 5625, 2048 },
>> > +  { 176400, LC_270M, 9375, 3136 },
>

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-12 Thread Zhang, Keqiao 
Tested by: Keqiao, Zhang <keqiao.zh...@intel.com>

-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Nikula, Jani
Sent: Monday, October 10, 2016 11:04 PM
To: intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com; Pandiyan, 
Dhinakaran <dhinakaran.pandi...@intel.com>
Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

When modeset occurs and the LS_CLK is set to some special values in DP mode, 
the N/M need to be set manually if audio is playing. Otherwise the first 
several seconds may be silent in audio playback.

The relationship of Maud and Naud is expressed in the following equation:
Maud/Naud = 512 * fs / f_LS_Clk

Please refer VESA DisplayPort Standard spec for details.

Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h|   7 +++
 drivers/gpu/drm/i915/intel_audio.c | 100 -
 2 files changed, 105 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h 
index 595d196f753f..8d9dbc7d5b32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7359,6 +7359,13 @@ enum {
 #define _HSW_AUD_MISC_CTRL_B   0x65110
 #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe, 
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
 
+#define _HSW_AUD_M_CTS_ENABLE_A0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B0x65128
+#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
+#define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
+#define   AUD_CONFIG_M_MASK0xf
+
 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 81df29ca4947..0bc2701b6c9c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -57,6 +57,70 @@
  * struct _audio_component_audio_ops @audio_ops is called from i915 
driver.
  */
 
+/* DP N/M table */
+#define LC_540M 54
+#define LC_270M 27
+#define LC_162M 162000
+
+struct dp_aud_n_m {
+   int sample_rate;
+   int clock;
+   u16 n;
+   u16 m;
+};
+
+static const struct dp_aud_n_m dp_aud_n_m[] = {
+   { 192000, LC_540M, 5625, 1024 },
+   { 176400, LC_540M, 9375, 1568 },
+   { 96000, LC_540M, 5625, 512 },
+   { 88200, LC_540M, 9375, 784 },
+   { 48000, LC_540M, 5625, 256 },
+   { 44100, LC_540M, 9375, 392 },
+   { 32000, LC_540M, 16875, 512 },
+   { 192000, LC_270M, 5625, 2048 },
+   { 176400, LC_270M, 9375, 3136 },
+   { 96000, LC_270M, 5625, 1024 },
+   { 88200, LC_270M, 9375, 1568 },
+   { 48000, LC_270M, 5625, 512 },
+   { 44100, LC_270M, 9375, 784 },
+   { 32000, LC_270M, 16875, 1024 },
+   { 192000, LC_162M, 3375, 2048 },
+   { 176400, LC_162M, 5625, 3136 },
+   { 96000, LC_162M, 3375, 1024 },
+   { 88200, LC_162M, 5625, 1568 },
+   { 48000, LC_162M, 3375, 512 },
+   { 44100, LC_162M, 5625, 784 },
+   { 32000, LC_162M, 10125, 1024 },
+};
+
+static const struct dp_aud_n_m *
+audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate) {
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
+   if (rate == dp_aud_n_m[i].sample_rate &&
+   intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
+   return _aud_n_m[i];
+   }
+
+   return NULL;
+}
+
+static int audio_config_dp_get_m(struct intel_crtc *intel_crtc, int 
+rate) {
+   const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, 
+rate);
+
+   return nm ? nm->m : 0;
+}
+
+static int audio_config_dp_get_n(struct intel_crtc *intel_crtc, int 
+rate) {
+   const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, 
+rate);
+
+   return nm ? nm->n : 0;
+}
+
 static const struct {
int clock;
u32 config;
@@ -225,8 +289,10 @@ hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, 
enum port port,
   const struct drm_display_mode *adjusted_mode)  {
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+   struct i915_audio_component *acomp = dev_priv->audio_component;
+   int rate = acomp ? acomp->aud_sample_rate[port] : 0;
enum pipe pipe = intel_crtc->pipe;
-   u32 tmp;
+   u32 tmp, n, m;
 
tmp = I915_READ(HSW_AUD_CFG(pipe));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
@@ -234,7 +300,30 @@ hsw_d

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-12 Thread Yang, Libin 


> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Lin, Mengdong
> Sent: Wednesday, October 12, 2016 10:46 AM
> To: Nikula, Jani <jani.nik...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
> Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> 
> 
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf Of Jani Nikula
> > Sent: Monday, October 10, 2016 11:04 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
> > Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> > modeset
> >
> > When modeset occurs and the LS_CLK is set to some special values in DP
> > mode, the N/M need to be set manually if audio is playing. Otherwise
> > the first several seconds may be silent in audio playback.
> >
> > The relationship of Maud and Naud is expressed in the following equation:
> > Maud/Naud = 512 * fs / f_LS_Clk
> >
> > Please refer VESA DisplayPort Standard spec for details.
> >
> > Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
> >  drivers/gpu/drm/i915/intel_audio.c | 100
> > -
> >  2 files changed, 105 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7359,6 +7359,13 @@ enum {
> >  #define _HSW_AUD_MISC_CTRL_B   0x65110
> >  #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> >
> > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > +#define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
> > +#define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
> > +#define   AUD_CONFIG_M_MASK0xf
> 
> The last line cause misalignment after applying the patch.
> 
> > +
> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
> >  #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) diff --
> git
> > a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 81df29ca4947..0bc2701b6c9c 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -57,6 +57,70 @@
> >   * struct _audio_component_audio_ops @audio_ops is called from
> > i915 driver.
> >   */
> >
> > +/* DP N/M table */
> > +#define LC_540M 54
> > +#define LC_270M 27
> > +#define LC_162M 162000
> > +
> > +struct dp_aud_n_m {
> > +   int sample_rate;
> > +   int clock;
> > +   u16 n;
> > +   u16 m;
> > +};
> > +
> > +static const struct dp_aud_n_m dp_aud_n_m[] = {
> > +   { 192000, LC_540M, 5625, 1024 },
> > +   { 176400, LC_540M, 9375, 1568 },
> > +   { 96000, LC_540M, 5625, 512 },
> > +   { 88200, LC_540M, 9375, 784 },
> > +   { 48000, LC_540M, 5625, 256 },
> > +   { 44100, LC_540M, 9375, 392 },
> > +   { 32000, LC_540M, 16875, 512 },
> > +   { 192000, LC_270M, 5625, 2048 },
> > +   { 176400, LC_270M, 9375, 3136 },
> > +   { 96000, LC_270M, 5625, 1024 },
> > +   { 88200, LC_270M, 9375, 1568 },
> > +   { 48000, LC_270M, 5625, 512 },
> > +   { 44100, LC_270M, 9375, 784 },
> > +   { 32000, LC_270M, 16875, 1024 },
> > +   { 192000, LC_162M, 3375, 2048 },
> > +   { 176400, LC_162M, 5625, 3136 },
> > +   { 96000, LC_162M, 3375, 1024 },
> > +   { 88200, LC_162M, 5625, 1568 },
> > +   { 48000, LC_162M, 3375, 512 },
> > +   { 44100, LC_162M, 5625, 784 },
> > +   { 32000, LC_162M, 10125, 1024 },
> > +};
> > +
> > +static const struct dp_aud_n_m *
> > +audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate) {
> &

Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-11 Thread Lin, Mengdong 


> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jani Nikula
> Sent: Monday, October 10, 2016 11:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nik...@intel.com>; libin.y...@linux.intel.com;
> Pandiyan, Dhinakaran <dhinakaran.pandi...@intel.com>
> Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> When modeset occurs and the LS_CLK is set to some special values in DP
> mode, the N/M need to be set manually if audio is playing. Otherwise the
> first several seconds may be silent in audio playback.
> 
> The relationship of Maud and Naud is expressed in the following equation:
> Maud/Naud = 512 * fs / f_LS_Clk
> 
> Please refer VESA DisplayPort Standard spec for details.
> 
> Signed-off-by: Libin Yang <libin.y...@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h|   7 +++
>  drivers/gpu/drm/i915/intel_audio.c | 100
> -
>  2 files changed, 105 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7359,6 +7359,13 @@ enum {
>  #define _HSW_AUD_MISC_CTRL_B 0x65110
>  #define HSW_AUD_MISC_CTRL(pipe)  _MMIO_PIPE(pipe,
> _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> 
> +#define _HSW_AUD_M_CTS_ENABLE_A  0x65028
> +#define _HSW_AUD_M_CTS_ENABLE_B  0x65128
> +#define HSW_AUD_M_CTS_ENABLE(pipe)   _MMIO_PIPE(pipe,
> _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> +#define   AUD_M_CTS_M_VALUE_INDEX(1 << 21)
> +#define   AUD_M_CTS_M_PROG_ENABLE(1 << 20)
> +#define   AUD_CONFIG_M_MASK  0xf

The last line cause misalignment after applying the patch.

> +
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_A   0x650b4
>  #define _HSW_AUD_DIP_ELD_CTRL_ST_B   0x651b4
>  #define HSW_AUD_DIP_ELD_CTRL(pipe)   _MMIO_PIPE(pipe,
> _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index 81df29ca4947..0bc2701b6c9c 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -57,6 +57,70 @@
>   * struct _audio_component_audio_ops @audio_ops is called from
> i915 driver.
>   */
> 
> +/* DP N/M table */
> +#define LC_540M 54
> +#define LC_270M 27
> +#define LC_162M 162000
> +
> +struct dp_aud_n_m {
> + int sample_rate;
> + int clock;
> + u16 n;
> + u16 m;
> +};
> +
> +static const struct dp_aud_n_m dp_aud_n_m[] = {
> + { 192000, LC_540M, 5625, 1024 },
> + { 176400, LC_540M, 9375, 1568 },
> + { 96000, LC_540M, 5625, 512 },
> + { 88200, LC_540M, 9375, 784 },
> + { 48000, LC_540M, 5625, 256 },
> + { 44100, LC_540M, 9375, 392 },
> + { 32000, LC_540M, 16875, 512 },
> + { 192000, LC_270M, 5625, 2048 },
> + { 176400, LC_270M, 9375, 3136 },
> + { 96000, LC_270M, 5625, 1024 },
> + { 88200, LC_270M, 9375, 1568 },
> + { 48000, LC_270M, 5625, 512 },
> + { 44100, LC_270M, 9375, 784 },
> + { 32000, LC_270M, 16875, 1024 },
> + { 192000, LC_162M, 3375, 2048 },
> + { 176400, LC_162M, 5625, 3136 },
> + { 96000, LC_162M, 3375, 1024 },
> + { 88200, LC_162M, 5625, 1568 },
> + { 48000, LC_162M, 3375, 512 },
> + { 44100, LC_162M, 5625, 784 },
> + { 32000, LC_162M, 10125, 1024 },
> +};
> +
> +static const struct dp_aud_n_m *
> +audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate) {
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
> + if (rate == dp_aud_n_m[i].sample_rate &&
> + intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
> + return _aud_n_m[i];
> + }
> +
> + return NULL;
> +}
> +
> +static int audio_config_dp_get_m(struct intel_crtc *intel_crtc, int
> +rate) {
> + const struct dp_aud_n_m *nm =
> audio_config_dp_get_n_m(intel_crtc,
> +rate);
> +
> + return nm ? nm->m : 0;
> +}
> +
> +static int audio_config_dp_get_n(struct intel_crtc *intel_crtc, int
> +rate) {
> + const struct dp_aud_n_m *nm =
> audio_config_dp_get_n_m(intel_crtc,
> +rate);
> +
> + return nm ? nm->n : 0;
> +}
> +
>  static const struct {
>   int clock;
>   u32 config;
> @@ -225,8 +289,10 @@ hsw_dp_audio_config_update(struct intel_

[Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

2016-10-10 Thread Jani Nikula 
When modeset occurs and the LS_CLK is set to some
special values in DP mode, the N/M need to be set
manually if audio is playing. Otherwise the first
several seconds may be silent in audio playback.

The relationship of Maud and Naud is expressed in
the following equation:
Maud/Naud = 512 * fs / f_LS_Clk

Please refer VESA DisplayPort Standard spec for details.

Signed-off-by: Libin Yang 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_reg.h|   7 +++
 drivers/gpu/drm/i915/intel_audio.c | 100 -
 2 files changed, 105 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 595d196f753f..8d9dbc7d5b32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7359,6 +7359,13 @@ enum {
 #define _HSW_AUD_MISC_CTRL_B   0x65110
 #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe, 
_HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
 
+#define _HSW_AUD_M_CTS_ENABLE_A0x65028
+#define _HSW_AUD_M_CTS_ENABLE_B0x65128
+#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
+#define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
+#define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
+#define   AUD_CONFIG_M_MASK0xf
+
 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, 
_HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 81df29ca4947..0bc2701b6c9c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -57,6 +57,70 @@
  * struct _audio_component_audio_ops @audio_ops is called from i915 
driver.
  */
 
+/* DP N/M table */
+#define LC_540M 54
+#define LC_270M 27
+#define LC_162M 162000
+
+struct dp_aud_n_m {
+   int sample_rate;
+   int clock;
+   u16 n;
+   u16 m;
+};
+
+static const struct dp_aud_n_m dp_aud_n_m[] = {
+   { 192000, LC_540M, 5625, 1024 },
+   { 176400, LC_540M, 9375, 1568 },
+   { 96000, LC_540M, 5625, 512 },
+   { 88200, LC_540M, 9375, 784 },
+   { 48000, LC_540M, 5625, 256 },
+   { 44100, LC_540M, 9375, 392 },
+   { 32000, LC_540M, 16875, 512 },
+   { 192000, LC_270M, 5625, 2048 },
+   { 176400, LC_270M, 9375, 3136 },
+   { 96000, LC_270M, 5625, 1024 },
+   { 88200, LC_270M, 9375, 1568 },
+   { 48000, LC_270M, 5625, 512 },
+   { 44100, LC_270M, 9375, 784 },
+   { 32000, LC_270M, 16875, 1024 },
+   { 192000, LC_162M, 3375, 2048 },
+   { 176400, LC_162M, 5625, 3136 },
+   { 96000, LC_162M, 3375, 1024 },
+   { 88200, LC_162M, 5625, 1568 },
+   { 48000, LC_162M, 3375, 512 },
+   { 44100, LC_162M, 5625, 784 },
+   { 32000, LC_162M, 10125, 1024 },
+};
+
+static const struct dp_aud_n_m *
+audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
+   if (rate == dp_aud_n_m[i].sample_rate &&
+   intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
+   return _aud_n_m[i];
+   }
+
+   return NULL;
+}
+
+static int audio_config_dp_get_m(struct intel_crtc *intel_crtc, int rate)
+{
+   const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate);
+
+   return nm ? nm->m : 0;
+}
+
+static int audio_config_dp_get_n(struct intel_crtc *intel_crtc, int rate)
+{
+   const struct dp_aud_n_m *nm = audio_config_dp_get_n_m(intel_crtc, rate);
+
+   return nm ? nm->n : 0;
+}
+
 static const struct {
int clock;
u32 config;
@@ -225,8 +289,10 @@ hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, 
enum port port,
   const struct drm_display_mode *adjusted_mode)
 {
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+   struct i915_audio_component *acomp = dev_priv->audio_component;
+   int rate = acomp ? acomp->aud_sample_rate[port] : 0;
enum pipe pipe = intel_crtc->pipe;
-   u32 tmp;
+   u32 tmp, n, m;
 
tmp = I915_READ(HSW_AUD_CFG(pipe));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
@@ -234,7 +300,30 @@ hsw_dp_audio_config_update(struct intel_crtc *intel_crtc, 
enum port port,
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
tmp |= AUD_CONFIG_N_VALUE_INDEX;
 
+   if (intel_crtc->config->port_clock == LC_540M ||
+   intel_crtc->config->port_clock == LC_270M ||
+   intel_crtc->config->port_clock == LC_162M) {
+   n = audio_config_dp_get_n(intel_crtc, rate);
+   if (n != 0) {
+   tmp &= ~AUD_CONFIG_N_MASK;
+   tmp |= AUD_CONFIG_N(n);
+   tmp |=