Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: whitelist needed predicate registers for Anv

2019-01-12 Thread Lionel Landwerlin 

On 12/01/2019 00:02, Lionel Landwerlin wrote:

On 11/01/2019 18:40, Lionel Landwerlin wrote:

There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.

v2: Define MI_PREDICATE_DATA_UDW (Lionel)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
  drivers/gpu/drm/i915/i915_reg.h    | 3 +++
  2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c

index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor 
gen7_render_regs[] = {

  REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
  REG64(MI_PREDICATE_SRC0),
  REG64(MI_PREDICATE_SRC1),
+    REG64(MI_PREDICATE_DATA),
+    REG32(MI_PREDICATE_RESULT),



As Ville mentioned on IRC, I should probably add RESULT_2 too.



Actually not quite sure, now that I see it must be programmed properly 
specially for GT3...


And it's not particularly useful.


Opinions?


Thanks,


-

Lionel






  REG32(GEN7_3DPRIM_END_OFFSET),
  REG32(GEN7_3DPRIM_START_VERTEX),
  REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct 
drm_i915_private *dev_priv)

   *    the parser enabled.
   * 9. Don't whitelist or handle oacontrol specially, as ownership
   *    for oacontrol state is moving to i915-perf.
+ * 10. Whitelist predicate data/result registers for conditional
+ * rendering in Anv.
   */
-    return 9;
+    return 10;
  }
diff --git a/drivers/gpu/drm/i915/i915_reg.h 
b/drivers/gpu/drm/i915/i915_reg.h

index ca8026ec0655..408dd59cdbdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t 
reg)

  #define MI_PREDICATE_SRC0_UDW    _MMIO(0x2400 + 4)
  #define MI_PREDICATE_SRC1    _MMIO(0x2408)
  #define MI_PREDICATE_SRC1_UDW    _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA    _MMIO(0x2410)
+#define MI_PREDICATE_DATA_UDW    _MMIO(0x2414)
+#define MI_PREDICATE_RESULT    _MMIO(0x2418)
    #define MI_PREDICATE_RESULT_2    _MMIO(0x2214)
  #define  LOWER_SLICE_ENABLED    (1 << 0)



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Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: whitelist needed predicate registers for Anv

2019-01-11 Thread Lionel Landwerlin 

On 11/01/2019 18:40, Lionel Landwerlin wrote:

There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.

v2: Define MI_PREDICATE_DATA_UDW (Lionel)

Signed-off-by: Lionel Landwerlin 
---
  drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
  drivers/gpu/drm/i915/i915_reg.h| 3 +++
  2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor 
gen7_render_regs[] = {
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
+   REG64(MI_PREDICATE_DATA),
+   REG32(MI_PREDICATE_RESULT),



As Ville mentioned on IRC, I should probably add RESULT_2 too.



REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private 
*dev_priv)
 *the parser enabled.
 * 9. Don't whitelist or handle oacontrol specially, as ownership
 *for oacontrol state is moving to i915-perf.
+* 10. Whitelist predicate data/result registers for conditional
+* rendering in Anv.
 */
-   return 9;
+   return 10;
  }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca8026ec0655..408dd59cdbdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
  #define MI_PREDICATE_SRC1 _MMIO(0x2408)
  #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA  _MMIO(0x2410)
+#define MI_PREDICATE_DATA_UDW  _MMIO(0x2414)
+#define MI_PREDICATE_RESULT_MMIO(0x2418)
  
  #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)

  #define  LOWER_SLICE_ENABLED  (1 << 0)



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[Intel-gfx] [PATCH v2] drm/i915/cmdparser: whitelist needed predicate registers for Anv

2019-01-11 Thread Lionel Landwerlin 
There is no reason not to whitelist those registers. In particular
MI_PREDICATE_RESULT can be loaded outside of MI_PREDICATE through
other registers to predicate other commands.

v2: Define MI_PREDICATE_DATA_UDW (Lionel)

Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +-
 drivers/gpu/drm/i915/i915_reg.h| 3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..c5bf14c3f540 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -549,6 +549,8 @@ static const struct drm_i915_reg_descriptor 
gen7_render_regs[] = {
REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
+   REG64(MI_PREDICATE_DATA),
+   REG32(MI_PREDICATE_RESULT),
REG32(GEN7_3DPRIM_END_OFFSET),
REG32(GEN7_3DPRIM_START_VERTEX),
REG32(GEN7_3DPRIM_VERTEX_COUNT),
@@ -1382,6 +1384,8 @@ int i915_cmd_parser_get_version(struct drm_i915_private 
*dev_priv)
 *the parser enabled.
 * 9. Don't whitelist or handle oacontrol specially, as ownership
 *for oacontrol state is moving to i915-perf.
+* 10. Whitelist predicate data/result registers for conditional
+* rendering in Anv.
 */
-   return 9;
+   return 10;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ca8026ec0655..408dd59cdbdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MI_PREDICATE_SRC0_UDW  _MMIO(0x2400 + 4)
 #define MI_PREDICATE_SRC1  _MMIO(0x2408)
 #define MI_PREDICATE_SRC1_UDW  _MMIO(0x2408 + 4)
+#define MI_PREDICATE_DATA  _MMIO(0x2410)
+#define MI_PREDICATE_DATA_UDW  _MMIO(0x2414)
+#define MI_PREDICATE_RESULT_MMIO(0x2418)
 
 #define MI_PREDICATE_RESULT_2  _MMIO(0x2214)
 #define  LOWER_SLICE_ENABLED   (1 << 0)
-- 
2.20.1

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