Re: [Intel-gfx] [PATCH v2 01/13] drm/i915/mtl: C20 PLL programming
On Fri, Apr 28, 2023 at 12:54:21PM +0300, Mika Kahola wrote:
> C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
> HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
> 4 lane support for c20.
>
> v2: Add 6.48Gbps and 6.75Gbps modes for eDP (RK)
> Fix lane check (RK)
> Fix multiline commenting (Arun)
> use usleep_range() instead of msleep() (Andi)
>
> Reviewed-by: Arun R Murthy
LGTM,
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Mika Kahola
> Signed-off-by: Bhanuprakash Modem
> Signed-off-by: Imre Deak
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 288 +++---
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 33 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h| 15 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> 5 files changed, 309 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 83180074b512..71163bc5bbf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private
> *i915, enum port port,
> __intel_cx0_write(i915, port, lane, addr, data, committed);
> }
>
> +static void intel_c20_sram_write(struct drm_i915_private *i915, enum port
> port,
> + int lane, u16 addr, u16 data)
> +{
> + assert_dc_off(i915);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
> +
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
> + intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
> +}
> +
> static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> int lane, u16 addr, u8 clear, u8 set, bool
> committed)
> {
> @@ -1415,6 +1427,215 @@ void intel_c10pll_dump_hw_state(struct
> drm_i915_private *i915,
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i
> + 3]);
> }
>
> +static bool intel_c20_use_mplla(u32 clock)
> +{
> + /* 10G and 20G rates use MPLLA */
> + if (clock == 312500 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static u8 intel_c20_get_dp_rate(u32 clock)
> +{
> + switch (clock) {
> + case 162000: /* 1.62 Gbps DP1.4 */
> + return 0;
> + case 27: /* 2.7 Gbps DP1.4 */
> + return 1;
> + case 54: /* 5.4 Gbps DP 1.4 */
> + return 2;
> + case 81: /* 8.1 Gbps DP1.4 */
> + return 3;
> + case 216000: /* 2.16 Gbps eDP */
> + return 4;
> + case 243000: /* 2.43 Gbps eDP */
> + return 5;
> + case 324000: /* 3.24 Gbps eDP */
> + return 6;
> + case 432000: /* 4.32 Gbps eDP */
> + return 7;
> + case 312500: /* 10 Gbps DP2.0 */
> + return 8;
> + case 421875: /* 13.5 Gbps DP2.0 */
> + return 9;
> + case 625000: /* 20 Gbps DP2.0*/
> + return 10;
> + case 648000: /* 6.48 Gbps eDP*/
> + return 11;
> + case 675000: /* 6.75 Gbps eDP*/
> + return 12;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static u8 intel_c20_get_hdmi_rate(u32 clock)
> +{
> + switch (clock) {
> + case 25175:
> + case 27000:
> + case 74250:
> + case 148500:
> + case 594000:
> + return 0;
> + case 166670: /* 3 Gbps */
> + case 30: /* 6 Gbps */
> + case 70: /* 12 Gbps */
> + return 1;
> + case 40: /* 8 Gbps */
> + return 2;
> + case 60: /* 10 Gbps */
> + return 3;
> + default:
> + MISSING_CASE(clock);
> + return 0;
> + }
> +}
> +
> +static bool is_dp2(u32 clock)
> +{
> + /* DP2.0 clock rates */
> + if (clock == 312500 || clock == 421875 || clock == 625000)
> + return true;
> +
> + return false;
> +}
> +
> +static bool is_hdmi_frl(u32 clock)
> +{
> + switch (clock) {
> + case 166670: /* 3 Gbps */
> + case 30: /* 6 Gbps */
> + case 40: /* 8 Gbps */
> + case 60: /* 10 Gbps */
> + case 70: /* 12 Gbps */
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> +
> + /* banks should not be cleared for DPALT/USB4/TBT modes */
> + /* TODO: optimize re-calibration in legacy mode */
> + return
[Intel-gfx] [PATCH v2 01/13] drm/i915/mtl: C20 PLL programming
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
v2: Add 6.48Gbps and 6.75Gbps modes for eDP (RK)
Fix lane check (RK)
Fix multiline commenting (Arun)
use usleep_range() instead of msleep() (Andi)
Reviewed-by: Arun R Murthy
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 288 +++---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 33 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
.../drm/i915/display/intel_display_types.h| 15 +-
drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
5 files changed, 309 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 83180074b512..71163bc5bbf5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -273,6 +273,18 @@ static void intel_cx0_write(struct drm_i915_private *i915,
enum port port,
__intel_cx0_write(i915, port, lane, addr, data, committed);
}
+static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
+int lane, u16 addr, u16 data)
+{
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool
committed)
{
@@ -1415,6 +1427,215 @@ void intel_c10pll_dump_hw_state(struct drm_i915_private
*i915,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i
+ 3]);
}
+static bool intel_c20_use_mplla(u32 clock)
+{
+ /* 10G and 20G rates use MPLLA */
+ if (clock == 312500 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static u8 intel_c20_get_dp_rate(u32 clock)
+{
+ switch (clock) {
+ case 162000: /* 1.62 Gbps DP1.4 */
+ return 0;
+ case 27: /* 2.7 Gbps DP1.4 */
+ return 1;
+ case 54: /* 5.4 Gbps DP 1.4 */
+ return 2;
+ case 81: /* 8.1 Gbps DP1.4 */
+ return 3;
+ case 216000: /* 2.16 Gbps eDP */
+ return 4;
+ case 243000: /* 2.43 Gbps eDP */
+ return 5;
+ case 324000: /* 3.24 Gbps eDP */
+ return 6;
+ case 432000: /* 4.32 Gbps eDP */
+ return 7;
+ case 312500: /* 10 Gbps DP2.0 */
+ return 8;
+ case 421875: /* 13.5 Gbps DP2.0 */
+ return 9;
+ case 625000: /* 20 Gbps DP2.0*/
+ return 10;
+ case 648000: /* 6.48 Gbps eDP*/
+ return 11;
+ case 675000: /* 6.75 Gbps eDP*/
+ return 12;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static u8 intel_c20_get_hdmi_rate(u32 clock)
+{
+ switch (clock) {
+ case 25175:
+ case 27000:
+ case 74250:
+ case 148500:
+ case 594000:
+ return 0;
+ case 166670: /* 3 Gbps */
+ case 30: /* 6 Gbps */
+ case 70: /* 12 Gbps */
+ return 1;
+ case 40: /* 8 Gbps */
+ return 2;
+ case 60: /* 10 Gbps */
+ return 3;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static bool is_dp2(u32 clock)
+{
+ /* DP2.0 clock rates */
+ if (clock == 312500 || clock == 421875 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static bool is_hdmi_frl(u32 clock)
+{
+ switch (clock) {
+ case 166670: /* 3 Gbps */
+ case 30: /* 6 Gbps */
+ case 40: /* 8 Gbps */
+ case 60: /* 10 Gbps */
+ case 70: /* 12 Gbps */
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+
+ /* banks should not be cleared for DPALT/USB4/TBT modes */
+ /* TODO: optimize re-calibration in legacy mode */
+ return intel_tc_port_in_legacy_mode(intel_dig_port);
+}
+
+static int intel_get_c20_custom_width(u32 clock, bool dp)
+{
+ if (dp && is_dp2(clock))
+ return 2;
+ else if (is_hdmi_frl(clock))
+ return 1;
+ else
+
