On Thu, Jan 05, 2023 at 02:54:29PM +0200, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
>
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, January 9, 2023 11:50 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre ; Sripada, Radhakrishna
> ; Kahola, Mika ;
> Shankar, Uma
> Subject: Re: [PATCH v2 04/21] drm/i915/mtl: Add Support for C10 PHY message
On Thu, 05 Jan 2023, Mika Kahola wrote:
> +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port
> port, int lane, u32 *val)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + if (__intel_wait_for_register(>uncore,
There's now an __intel_de_ variant of
On Thu, 05 Jan 2023, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
> XELPDP has C10 phys to
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from
