Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-07 Thread Manasi Navare
On Wed, Sep 07, 2016 at 12:47:49PM +0300, Mika Kahola wrote: > On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower lane count

Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-07 Thread Jim Bride
On Wed, Sep 07, 2016 at 12:47:49PM +0300, Mika Kahola wrote: > On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote: > > According to the DisplayPort Spec, in case of Clock Recovery failure > > the link training sequence should fall back to the lower link rate > > followed by lower lane count

Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-07 Thread Mika Kahola
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote: > According to the DisplayPort Spec, in case of Clock Recovery failure > the link training sequence should fall back to the lower link rate > followed by lower lane count until CR succeeds. > On CR success, the sequence proceeds with Channel

[Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training

2016-09-06 Thread Manasi Navare
According to the DisplayPort Spec, in case of Clock Recovery failure the link training sequence should fall back to the lower link rate followed by lower lane count until CR succeeds. On CR success, the sequence proceeds with Channel EQ. In case of Channel EQ failures, it should fallback to lower