Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
> -Original Message- > From: Srinivas, Vidya > Sent: Wednesday, May 25, 2022 2:50 PM > To: Jani Nikula ; Souza, Jose > ; intel-gfx@lists.freedesktop.org > Cc: Sean Paul ; Syrjala, Ville > > Subject: RE: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless > mode switch > > > > > -Original Message- > > From: Jani Nikula > > Sent: Wednesday, May 25, 2022 2:26 PM > > To: Srinivas, Vidya ; Souza, Jose > > ; intel-gfx@lists.freedesktop.org > > Cc: Sean Paul ; Syrjala, Ville > > > > Subject: Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement > > seamless mode switch > > > > On Wed, 25 May 2022, "Srinivas, Vidya" wrote: > > > Hello, > > > > > > Apologies for bothering. May we kindly know if this solution is approved? > > > I have provided the Tested-by. Thanks much. > > > > IIUC the more complete solution is [1]. > > > > BR, > > Jani. > > > > > > [1] https://patchwork.freedesktop.org/series/103491/ > > > Hello Jani, > > Thank you very much. I will have a check of this. > For user space triggered seamless modeset WITHOUT setting > "DRM_MODE_ATOMIC_ALLOW_MODESET", for switch between 2 refresh > rates, Jose patches is working. > Jose please correct me if I am wrong. Thank you. > > Regards > Vidya Hello Jani, I checked the new series https://patchwork.freedesktop.org/series/103491/ and this is working as well. I tested it on ADL-P RVP with 144/60Hz panel. Both solutions from Jose and Ville are working. Many thanks to both. Regards Vidya > > > > > > > > > > Regards > > > Vidya > > > > > >> -Original Message- > > >> From: Srinivas, Vidya > > >> Sent: Monday, May 9, 2022 8:44 PM > > >> To: Souza, Jose ; > > >> intel-gfx@lists.freedesktop.org > > >> Cc: Sean Paul ; Ville Syrjälä > > >> > > >> Subject: RE: [PATCH v2 3/3] drm/i915/display: Implement seamless > > >> mode switch > > >> > > >> Hello Jose, > > >> > > >> Thanks much for the patch. I tested it on chrome system and the > > >> patch works. > > >> Adding my Tested-by. > > >> Tested-by: Vidya Srinivas > > >> > > >> Regards > > >> Vidya > > >> > > >> > -Original Message- > > >> > From: Souza, Jose > > >> > Sent: Tuesday, May 3, 2022 2:11 AM > > >> > To: intel-gfx@lists.freedesktop.org > > >> > Cc: Srinivas, Vidya ; Sean Paul > > >> > ; Ville Syrjälä > > >> > ; Souza, Jose > > >> > > > >> > Subject: [PATCH v2 3/3] drm/i915/display: Implement seamless mode > > >> > switch > > >> > > > >> > So far the i915's DRRS feature was automatically changing between > > >> > preferred panel mode and downclock mode based on idleness but > > >> ChromeOS > > >> > compositor team is asking to be in control of the mode switch. > > >> > So for certain types of content it can switch to a mode with a > > >> > lower refresh rate without the user noticing a thing and saving > > >> > more > > power. > > >> > > > >> > This seamless mode switch will be triggered when user-space > > >> > dispatches an atomic commit with the new mode and clears the > > >> > DRM_MODE_ATOMIC_ALLOW_MODESET flag. > > >> > > > >> > The main steps to acomplish that are: > > >> > > > >> > - as mode changed in atomic state > > drm_atomic_helper_check_modeset() > > >> > will set mode_changed and it will trigger the crtc state > > >> > computation so > > >> > intel_dp_compute_config() will be called and dp_m_n will be > > >> > computed for the new mode > > >> > > > >> > - then intel_dp_drrs_compute_config() will check for the > > >> > necessary conditions to do a seamless mode switch, if possible > > >> > crtc_state- > > >> > >seamless_mode_switch will be set and has_drrs will not be set, > > >> > >so > > >> > >i915 will > > >> > not automatically switch between modes > > >> > > > >> > - then intel_crtc_compute_config() will call > > >> > intel_crtc_compute_pixel_rate() that will take the hint that i
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
> -Original Message- > From: Jani Nikula > Sent: Wednesday, May 25, 2022 2:26 PM > To: Srinivas, Vidya ; Souza, Jose > ; intel-gfx@lists.freedesktop.org > Cc: Sean Paul ; Syrjala, Ville > > Subject: Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless > mode switch > > On Wed, 25 May 2022, "Srinivas, Vidya" wrote: > > Hello, > > > > Apologies for bothering. May we kindly know if this solution is approved? > > I have provided the Tested-by. Thanks much. > > IIUC the more complete solution is [1]. > > BR, > Jani. > > > [1] https://patchwork.freedesktop.org/series/103491/ > Hello Jani, Thank you very much. I will have a check of this. For user space triggered seamless modeset WITHOUT setting "DRM_MODE_ATOMIC_ALLOW_MODESET", for switch between 2 refresh rates, Jose patches is working. Jose please correct me if I am wrong. Thank you. Regards Vidya > > > > > > Regards > > Vidya > > > >> -Original Message- > >> From: Srinivas, Vidya > >> Sent: Monday, May 9, 2022 8:44 PM > >> To: Souza, Jose ; > >> intel-gfx@lists.freedesktop.org > >> Cc: Sean Paul ; Ville Syrjälä > >> > >> Subject: RE: [PATCH v2 3/3] drm/i915/display: Implement seamless mode > >> switch > >> > >> Hello Jose, > >> > >> Thanks much for the patch. I tested it on chrome system and the patch > >> works. > >> Adding my Tested-by. > >> Tested-by: Vidya Srinivas > >> > >> Regards > >> Vidya > >> > >> > -Original Message- > >> > From: Souza, Jose > >> > Sent: Tuesday, May 3, 2022 2:11 AM > >> > To: intel-gfx@lists.freedesktop.org > >> > Cc: Srinivas, Vidya ; Sean Paul > >> > ; Ville Syrjälä > >> > ; Souza, Jose > >> > Subject: [PATCH v2 3/3] drm/i915/display: Implement seamless mode > >> > switch > >> > > >> > So far the i915's DRRS feature was automatically changing between > >> > preferred panel mode and downclock mode based on idleness but > >> ChromeOS > >> > compositor team is asking to be in control of the mode switch. > >> > So for certain types of content it can switch to a mode with a > >> > lower refresh rate without the user noticing a thing and saving more > power. > >> > > >> > This seamless mode switch will be triggered when user-space > >> > dispatches an atomic commit with the new mode and clears the > >> > DRM_MODE_ATOMIC_ALLOW_MODESET flag. > >> > > >> > The main steps to acomplish that are: > >> > > >> > - as mode changed in atomic state > drm_atomic_helper_check_modeset() > >> > will set mode_changed and it will trigger the crtc state > >> > computation so > >> > intel_dp_compute_config() will be called and dp_m_n will be > >> > computed for the new mode > >> > > >> > - then intel_dp_drrs_compute_config() will check for the necessary > >> > conditions to do a seamless mode switch, if possible crtc_state- > >> > >seamless_mode_switch will be set and has_drrs will not be set, so > >> > >i915 will > >> > not automatically switch between modes > >> > > >> > - then intel_crtc_compute_config() will call > >> > intel_crtc_compute_pixel_rate() that will take the hint that it is > >> > trying to do a seamless mode switch and set pixel_rate to the > >> > pixel_rate of the old state > >> > > >> > - then if nothing else changed in the state > >> > intel_crtc_check_fastset() will be able to set mode_changed to > >> > false and i915 can do fastset otherwise the commit will fail during > >> > the check phase > >> > > >> > - now on the atomic commit phase, intel_ddi_update_pipe_dp() will > >> > be called and will program the new dp_m_n > >> > > >> > - nothing else is different in the commit phase until the step to > >> > verify programmed state, the most important change here is that > >> > need to save the pixel_rate in DRRS global state as there is no > >> > other way to get that from hardware or atomic state > >> > > >> > v2: > >> > - not overwritten dp_m_n values in intel_crtc_copy_fastset() when > >> > doing a seamless_mode_switch > >> > > >> > Cc: Vidya Srinivas > >> &g
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
On Wed, 25 May 2022, "Srinivas, Vidya" wrote:
> Hello,
>
> Apologies for bothering. May we kindly know if this solution is approved?
> I have provided the Tested-by. Thanks much.
IIUC the more complete solution is [1].
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/103491/
>
> Regards
> Vidya
>
>> -Original Message-
>> From: Srinivas, Vidya
>> Sent: Monday, May 9, 2022 8:44 PM
>> To: Souza, Jose ; intel-gfx@lists.freedesktop.org
>> Cc: Sean Paul ; Ville Syrjälä
>>
>> Subject: RE: [PATCH v2 3/3] drm/i915/display: Implement seamless mode
>> switch
>>
>> Hello Jose,
>>
>> Thanks much for the patch. I tested it on chrome system and the patch
>> works.
>> Adding my Tested-by.
>> Tested-by: Vidya Srinivas
>>
>> Regards
>> Vidya
>>
>> > -Original Message-
>> > From: Souza, Jose
>> > Sent: Tuesday, May 3, 2022 2:11 AM
>> > To: intel-gfx@lists.freedesktop.org
>> > Cc: Srinivas, Vidya ; Sean Paul
>> > ; Ville Syrjälä
>> > ; Souza, Jose
>> > Subject: [PATCH v2 3/3] drm/i915/display: Implement seamless mode
>> > switch
>> >
>> > So far the i915's DRRS feature was automatically changing between
>> > preferred panel mode and downclock mode based on idleness but
>> ChromeOS
>> > compositor team is asking to be in control of the mode switch.
>> > So for certain types of content it can switch to a mode with a lower
>> > refresh rate without the user noticing a thing and saving more power.
>> >
>> > This seamless mode switch will be triggered when user-space dispatches
>> > an atomic commit with the new mode and clears the
>> > DRM_MODE_ATOMIC_ALLOW_MODESET flag.
>> >
>> > The main steps to acomplish that are:
>> >
>> > - as mode changed in atomic state drm_atomic_helper_check_modeset()
>> > will set mode_changed and it will trigger the crtc state computation
>> > so
>> > intel_dp_compute_config() will be called and dp_m_n will be computed
>> > for the new mode
>> >
>> > - then intel_dp_drrs_compute_config() will check for the necessary
>> > conditions to do a seamless mode switch, if possible crtc_state-
>> > >seamless_mode_switch will be set and has_drrs will not be set, so
>> > >i915 will
>> > not automatically switch between modes
>> >
>> > - then intel_crtc_compute_config() will call
>> > intel_crtc_compute_pixel_rate() that will take the hint that it is
>> > trying to do a seamless mode switch and set pixel_rate to the
>> > pixel_rate of the old state
>> >
>> > - then if nothing else changed in the state intel_crtc_check_fastset()
>> > will be able to set mode_changed to false and i915 can do fastset
>> > otherwise the commit will fail during the check phase
>> >
>> > - now on the atomic commit phase, intel_ddi_update_pipe_dp() will be
>> > called and will program the new dp_m_n
>> >
>> > - nothing else is different in the commit phase until the step to
>> > verify programmed state, the most important change here is that need
>> > to save the pixel_rate in DRRS global state as there is no other way
>> > to get that from hardware or atomic state
>> >
>> > v2:
>> > - not overwritten dp_m_n values in intel_crtc_copy_fastset() when
>> > doing a seamless_mode_switch
>> >
>> > Cc: Vidya Srinivas
>> > Cc: Sean Paul
>> > Cc: Ville Syrjälä
>> > Signed-off-by: José Roberto de Souza
>> > ---
>> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
>> > drivers/gpu/drm/i915/display/intel_display.c | 61
>> > --- .../drm/i915/display/intel_display_debugfs.c | 3 +
>> > .../drm/i915/display/intel_display_types.h| 3 +
>> > drivers/gpu/drm/i915/display/intel_dp.c | 56 ++---
>> > drivers/gpu/drm/i915/display/intel_drrs.c | 38 +---
>> > drivers/gpu/drm/i915/display/intel_drrs.h | 3 +
>> > 7 files changed, 151 insertions(+), 23 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > index 9e6fa59eabba7..732e5d425412e 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> > @@ -46,6 +46,7 @@
>> > #include "intel_dp_link_training.h"
>> > #include "intel_dp_mst.h"
>> > #include "intel_dpio_phy.h"
>> > +#include "intel_drrs.h"
>> > #include "intel_dsi.h"
>> > #include "intel_fdi.h"
>> > #include "intel_fifo_underrun.h"
>> > @@ -3010,6 +3011,14 @@ static void intel_ddi_update_pipe_dp(struct
>> > intel_atomic_state *state,
>> >
>> >intel_backlight_update(state, encoder, crtc_state, conn_state);
>> >drm_connector_update_privacy_screen(conn_state);
>> > +
>> > + if (crtc_state->seamless_mode_switch) {
>> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
>> > >uapi.crtc);
>> > +
>> > + intel_cpu_transcoder_set_m1_n1(intel_crtc,
>> > + crtc_state->cpu_transcoder,
>> > + _state->dp_m_n);
>> > + }
>> > }
>> >
>> > void intel_ddi_update_pipe(struct intel_atomic_state *state, @@
>> >
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
Hello,
Apologies for bothering. May we kindly know if this solution is approved?
I have provided the Tested-by. Thanks much.
Regards
Vidya
> -Original Message-
> From: Srinivas, Vidya
> Sent: Monday, May 9, 2022 8:44 PM
> To: Souza, Jose ; intel-gfx@lists.freedesktop.org
> Cc: Sean Paul ; Ville Syrjälä
>
> Subject: RE: [PATCH v2 3/3] drm/i915/display: Implement seamless mode
> switch
>
> Hello Jose,
>
> Thanks much for the patch. I tested it on chrome system and the patch
> works.
> Adding my Tested-by.
> Tested-by: Vidya Srinivas
>
> Regards
> Vidya
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Tuesday, May 3, 2022 2:11 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Srinivas, Vidya ; Sean Paul
> > ; Ville Syrjälä
> > ; Souza, Jose
> > Subject: [PATCH v2 3/3] drm/i915/display: Implement seamless mode
> > switch
> >
> > So far the i915's DRRS feature was automatically changing between
> > preferred panel mode and downclock mode based on idleness but
> ChromeOS
> > compositor team is asking to be in control of the mode switch.
> > So for certain types of content it can switch to a mode with a lower
> > refresh rate without the user noticing a thing and saving more power.
> >
> > This seamless mode switch will be triggered when user-space dispatches
> > an atomic commit with the new mode and clears the
> > DRM_MODE_ATOMIC_ALLOW_MODESET flag.
> >
> > The main steps to acomplish that are:
> >
> > - as mode changed in atomic state drm_atomic_helper_check_modeset()
> > will set mode_changed and it will trigger the crtc state computation
> > so
> > intel_dp_compute_config() will be called and dp_m_n will be computed
> > for the new mode
> >
> > - then intel_dp_drrs_compute_config() will check for the necessary
> > conditions to do a seamless mode switch, if possible crtc_state-
> > >seamless_mode_switch will be set and has_drrs will not be set, so
> > >i915 will
> > not automatically switch between modes
> >
> > - then intel_crtc_compute_config() will call
> > intel_crtc_compute_pixel_rate() that will take the hint that it is
> > trying to do a seamless mode switch and set pixel_rate to the
> > pixel_rate of the old state
> >
> > - then if nothing else changed in the state intel_crtc_check_fastset()
> > will be able to set mode_changed to false and i915 can do fastset
> > otherwise the commit will fail during the check phase
> >
> > - now on the atomic commit phase, intel_ddi_update_pipe_dp() will be
> > called and will program the new dp_m_n
> >
> > - nothing else is different in the commit phase until the step to
> > verify programmed state, the most important change here is that need
> > to save the pixel_rate in DRRS global state as there is no other way
> > to get that from hardware or atomic state
> >
> > v2:
> > - not overwritten dp_m_n values in intel_crtc_copy_fastset() when
> > doing a seamless_mode_switch
> >
> > Cc: Vidya Srinivas
> > Cc: Sean Paul
> > Cc: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
> > drivers/gpu/drm/i915/display/intel_display.c | 61
> > --- .../drm/i915/display/intel_display_debugfs.c | 3 +
> > .../drm/i915/display/intel_display_types.h| 3 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 56 ++---
> > drivers/gpu/drm/i915/display/intel_drrs.c | 38 +---
> > drivers/gpu/drm/i915/display/intel_drrs.h | 3 +
> > 7 files changed, 151 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 9e6fa59eabba7..732e5d425412e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -46,6 +46,7 @@
> > #include "intel_dp_link_training.h"
> > #include "intel_dp_mst.h"
> > #include "intel_dpio_phy.h"
> > +#include "intel_drrs.h"
> > #include "intel_dsi.h"
> > #include "intel_fdi.h"
> > #include "intel_fifo_underrun.h"
> > @@ -3010,6 +3011,14 @@ static void intel_ddi_update_pipe_dp(struct
> > intel_atomic_state *state,
> >
> > intel_backlight_update(state, encoder, crtc_state, conn_state);
> > drm_connector_update_privacy_screen(conn_state);
> > +
> > + if (crtc_state->seamless_mode_switch) {
> > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> > >uapi.crtc);
> > +
> > + intel_cpu_transcoder_set_m1_n1(intel_crtc,
> > + crtc_state->cpu_transcoder,
> > + _state->dp_m_n);
> > + }
> > }
> >
> > void intel_ddi_update_pipe(struct intel_atomic_state *state, @@
> > -3484,6
> > +3493,7 @@ static void intel_ddi_get_config(struct intel_encoder
> > +*encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> >
> > intel_psr_get_config(encoder, pipe_config);
> > + intel_drrs_get_config(encoder, pipe_config);
> > }
> >
> > void
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
Hello Jose,
Thanks much for the patch. I tested it on chrome system and the patch works.
Adding my Tested-by.
Tested-by: Vidya Srinivas
Regards
Vidya
> -Original Message-
> From: Souza, Jose
> Sent: Tuesday, May 3, 2022 2:11 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srinivas, Vidya ; Sean Paul
> ; Ville Syrjälä ;
> Souza, Jose
> Subject: [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
>
> So far the i915's DRRS feature was automatically changing between preferred
> panel mode and downclock mode based on idleness but ChromeOS
> compositor team is asking to be in control of the mode switch.
> So for certain types of content it can switch to a mode with a lower refresh
> rate without the user noticing a thing and saving more power.
>
> This seamless mode switch will be triggered when user-space dispatches an
> atomic commit with the new mode and clears the
> DRM_MODE_ATOMIC_ALLOW_MODESET flag.
>
> The main steps to acomplish that are:
>
> - as mode changed in atomic state drm_atomic_helper_check_modeset() will
> set mode_changed and it will trigger the crtc state computation so
> intel_dp_compute_config() will be called and dp_m_n will be computed for
> the new mode
>
> - then intel_dp_drrs_compute_config() will check for the necessary
> conditions to do a seamless mode switch, if possible crtc_state-
> >seamless_mode_switch will be set and has_drrs will not be set, so i915 will
> not automatically switch between modes
>
> - then intel_crtc_compute_config() will call
> intel_crtc_compute_pixel_rate() that will take the hint that it is trying to
> do a
> seamless mode switch and set pixel_rate to the pixel_rate of the old state
>
> - then if nothing else changed in the state intel_crtc_check_fastset() will be
> able to set mode_changed to false and i915 can do fastset otherwise the
> commit will fail during the check phase
>
> - now on the atomic commit phase, intel_ddi_update_pipe_dp() will be
> called and will program the new dp_m_n
>
> - nothing else is different in the commit phase until the step to verify
> programmed state, the most important change here is that need to save the
> pixel_rate in DRRS global state as there is no other way to get that from
> hardware or atomic state
>
> v2:
> - not overwritten dp_m_n values in intel_crtc_copy_fastset() when doing a
> seamless_mode_switch
>
> Cc: Vidya Srinivas
> Cc: Sean Paul
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
> drivers/gpu/drm/i915/display/intel_display.c | 61 ---
> .../drm/i915/display/intel_display_debugfs.c | 3 +
> .../drm/i915/display/intel_display_types.h| 3 +
> drivers/gpu/drm/i915/display/intel_dp.c | 56 ++---
> drivers/gpu/drm/i915/display/intel_drrs.c | 38 +---
> drivers/gpu/drm/i915/display/intel_drrs.h | 3 +
> 7 files changed, 151 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9e6fa59eabba7..732e5d425412e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -46,6 +46,7 @@
> #include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> +#include "intel_drrs.h"
> #include "intel_dsi.h"
> #include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> @@ -3010,6 +3011,14 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
> intel_backlight_update(state, encoder, crtc_state, conn_state);
> drm_connector_update_privacy_screen(conn_state);
> +
> + if (crtc_state->seamless_mode_switch) {
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
> +
> + intel_cpu_transcoder_set_m1_n1(intel_crtc,
> +crtc_state->cpu_transcoder,
> +_state->dp_m_n);
> + }
> }
>
> void intel_ddi_update_pipe(struct intel_atomic_state *state, @@ -3484,6
> +3493,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>
> intel_psr_get_config(encoder, pipe_config);
> + intel_drrs_get_config(encoder, pipe_config);
> }
>
> void intel_ddi_get_clock(struct intel_encoder *encoder, diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 17d0cad9e1686..e54fbe3b1d394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2629,6 +2629,44 @@ static void intel_crtc_compute_pixel_rate(struct
> intel_crtc_state *crtc_state)
> else
> crtc_state->pixel_rate =
> ilk_pipe_pixel_rate(crtc_state);
> +
> + /*
> + * Do not change pixel_rate when doing seamless mode switch,
>
[Intel-gfx] [PATCH v2 3/3] drm/i915/display: Implement seamless mode switch
So far the i915's DRRS feature was automatically changing between
preferred panel mode and downclock mode based on idleness but ChromeOS
compositor team is asking to be in control of the mode switch.
So for certain types of content it can switch to a mode with a lower
refresh rate without the user noticing a thing and saving more power.
This seamless mode switch will be triggered when user-space dispatches
an atomic commit with the new mode and clears the
DRM_MODE_ATOMIC_ALLOW_MODESET flag.
The main steps to acomplish that are:
- as mode changed in atomic state drm_atomic_helper_check_modeset()
will set mode_changed and it will trigger the crtc state computation
so intel_dp_compute_config() will be called and dp_m_n will be
computed for the new mode
- then intel_dp_drrs_compute_config() will check for the necessary
conditions to do a seamless mode switch, if possible
crtc_state->seamless_mode_switch will be set and has_drrs will not
be set, so i915 will not automatically switch between modes
- then intel_crtc_compute_config() will call
intel_crtc_compute_pixel_rate() that will take the hint that it is
trying to do a seamless mode switch and set pixel_rate to the
pixel_rate of the old state
- then if nothing else changed in the state intel_crtc_check_fastset()
will be able to set mode_changed to false and i915 can do fastset
otherwise the commit will fail during the check phase
- now on the atomic commit phase, intel_ddi_update_pipe_dp()
will be called and will program the new dp_m_n
- nothing else is different in the commit phase until the step to
verify programmed state, the most important change here is that need
to save the pixel_rate in DRRS global state as there is no other
way to get that from hardware or atomic state
v2:
- not overwritten dp_m_n values in intel_crtc_copy_fastset() when
doing a seamless_mode_switch
Cc: Vidya Srinivas
Cc: Sean Paul
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
drivers/gpu/drm/i915/display/intel_display.c | 61 ---
.../drm/i915/display/intel_display_debugfs.c | 3 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dp.c | 56 ++---
drivers/gpu/drm/i915/display/intel_drrs.c | 38 +---
drivers/gpu/drm/i915/display/intel_drrs.h | 3 +
7 files changed, 151 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9e6fa59eabba7..732e5d425412e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -46,6 +46,7 @@
#include "intel_dp_link_training.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
+#include "intel_drrs.h"
#include "intel_dsi.h"
#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
@@ -3010,6 +3011,14 @@ static void intel_ddi_update_pipe_dp(struct
intel_atomic_state *state,
intel_backlight_update(state, encoder, crtc_state, conn_state);
drm_connector_update_privacy_screen(conn_state);
+
+ if (crtc_state->seamless_mode_switch) {
+ struct intel_crtc *intel_crtc =
to_intel_crtc(crtc_state->uapi.crtc);
+
+ intel_cpu_transcoder_set_m1_n1(intel_crtc,
+ crtc_state->cpu_transcoder,
+ _state->dp_m_n);
+ }
}
void intel_ddi_update_pipe(struct intel_atomic_state *state,
@@ -3484,6 +3493,7 @@ static void intel_ddi_get_config(struct intel_encoder
*encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
intel_psr_get_config(encoder, pipe_config);
+ intel_drrs_get_config(encoder, pipe_config);
}
void intel_ddi_get_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 17d0cad9e1686..e54fbe3b1d394 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2629,6 +2629,44 @@ static void intel_crtc_compute_pixel_rate(struct
intel_crtc_state *crtc_state)
else
crtc_state->pixel_rate =
ilk_pipe_pixel_rate(crtc_state);
+
+ /*
+* Do not change pixel_rate when doing seamless mode switch, otherwise
+* it will change port_clock and other stuff that will need a modeset
+* to be programmed
+*/
+ if (crtc_state->seamless_mode_switch) {
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state;
+
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+
+ /*
+* It can only seamless switch if pixel rate of the new mode is
+
