[Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation

2014-02-07 Thread akash . goel
From: Akash Goel akash.g...@intel.com Modified programming of following 2 regs in Render ring initialisation fn. 1. GFX_MODE_GEN7 (Enabling TLB invalidate) 2. MI_MODE (Enabling MI Flush) v2: Removed the enabling of MI_FLUSH (Ville) Added new comments (Ville). Signed-off-by: Akash Goel

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation

2014-02-07 Thread Chris Wilson
On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.g...@intel.com wrote: From: Akash Goel akash.g...@intel.com Modified programming of following 2 regs in Render ring initialisation fn. 1. GFX_MODE_GEN7 (Enabling TLB invalidate) The changelog needs to explain why. According to the spec this is

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation

2014-02-07 Thread Goel, Akash
1. GFX_MODE_GEN7 (Enabling TLB invalidate) The changelog needs to explain why. According to the spec this is a pessimisation. Ok, Will look into this. 2. MI_MODE (Enabling MI Flush) And this is out-of-date. Doesn't describe the actual change nor why. Sorry I did not update the commit

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation

2014-02-07 Thread Ville Syrjälä
On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.g...@intel.com wrote: From: Akash Goel akash.g...@intel.com Modified programming of following 2 regs in Render ring initialisation fn. 1. GFX_MODE_GEN7 (Enabling TLB invalidate) 2. MI_MODE (Enabling MI Flush) v2: Removed the enabling of