Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
> -Original Message-
> From: Intel-gfx On Behalf Of
> Sripada,
> Radhakrishna
> Sent: Wednesday, November 22, 2023 10:49 PM
> To: Chauhan, Shekhar ; intel-
> g...@lists.freedesktop.org
> Cc: Roper, Matthew D
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
>
>
>
> > -Original Message-
> > From: Chauhan, Shekhar
> > Sent: Wednesday, November 22, 2023 10:34 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Roper, Matthew D ; Sripada, Radhakrishna
> > ; Chauhan, Shekhar
> >
> > Subject: [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
> >
> > Wa_22016670082 is applicable on GT and Media.
> > For GT, an MCR register is required instead of MMIO.
> >
> > v1: Introduce the fix.
> > v2: Minor naming convention change and adding a TODO
> > v3: Enhancing the TODO
> >
> LGTM,
> Reviewed-by: Radhakrishna Sripada
With actual r-b
Reviewed-by: Radhakrishna Sripada
>
> > Signed-off-by: Shekhar Chauhan
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > 2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 9de41703fae5..b2a245e3e77f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -529,7 +529,9 @@
> >
> > #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
> >
> > +/* TODO: Evaluate MCR usage for both Media and GT instances of SQCNT1
> > register. */
> > #define GEN12_SQCNT1 _MMIO(0x8718)
> > +#define GEN12_GT_SQCNT1MCR_REG(0x8718)
> > #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> > #define GEN12_SQCNT1_OABPC REG_BIT(29)
> > #define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 9bc0654efdc0..dbf0c6e536f1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> > i915_wa_list *wal)
> > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> >
> > /* Wa_22016670082 */
> > - wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > + wa_mcr_write_or(wal, GEN12_GT_SQCNT1,
> > GEN12_STRICT_RAR_ENABLE);
> >
> > if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > --
> > 2.34.1
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
> -Original Message-
> From: Chauhan, Shekhar
> Sent: Wednesday, November 22, 2023 10:34 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Sripada, Radhakrishna
> ; Chauhan, Shekhar
>
> Subject: [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
>
> Wa_22016670082 is applicable on GT and Media.
> For GT, an MCR register is required instead of MMIO.
>
> v1: Introduce the fix.
> v2: Minor naming convention change and adding a TODO
> v3: Enhancing the TODO
>
LGTM,
Reviewed-by: Radhakrishna Sripada
> Signed-off-by: Shekhar Chauhan
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 9de41703fae5..b2a245e3e77f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -529,7 +529,9 @@
>
> #define GEN8_RC6_CTX_INFO_MMIO(0x8504)
>
> +/* TODO: Evaluate MCR usage for both Media and GT instances of SQCNT1
> register. */
> #define GEN12_SQCNT1 _MMIO(0x8718)
> +#define GEN12_GT_SQCNT1 MCR_REG(0x8718)
> #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
> #define GEN12_SQCNT1_OABPC REG_BIT(29)
> #define GEN12_STRICT_RAR_ENABLEREG_BIT(23)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9bc0654efdc0..dbf0c6e536f1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> /* Wa_22016670082 */
> - wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> + wa_mcr_write_or(wal, GEN12_GT_SQCNT1,
> GEN12_STRICT_RAR_ENABLE);
>
> if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> --
> 2.34.1
[Intel-gfx] [PATCH v3] drm/i915/mtl: Fix Wa_22016670082
Wa_22016670082 is applicable on GT and Media.
For GT, an MCR register is required instead of MMIO.
v1: Introduce the fix.
v2: Minor naming convention change and adding a TODO
v3: Enhancing the TODO
Signed-off-by: Shekhar Chauhan
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 9de41703fae5..b2a245e3e77f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -529,7 +529,9 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
+/* TODO: Evaluate MCR usage for both Media and GT instances of SQCNT1
register. */
#define GEN12_SQCNT1 _MMIO(0x8718)
+#define GEN12_GT_SQCNT1MCR_REG(0x8718)
#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
#define GEN12_SQCNT1_OABPC REG_BIT(29)
#define GEN12_STRICT_RAR_ENABLE REG_BIT(23)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9bc0654efdc0..dbf0c6e536f1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_22016670082 */
- wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
+ wa_mcr_write_or(wal, GEN12_GT_SQCNT1, GEN12_STRICT_RAR_ENABLE);
if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
--
2.34.1
