Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-15 Thread Lucas De Marchi
On Tue, Nov 14, 2017 at 5:10 AM, Ville Syrjälä wrote: > On Mon, Nov 13, 2017 at 01:47:26PM -0800, Lucas De Marchi wrote: >> Hi Ville, >> >> On Thu, Nov 9, 2017 at 8:58 AM, Ville Syrjälä >> wrote: >> > On Thu, Nov 09, 2017 at 08:02:40AM -0800, Lucas De Marchi wrote: >> >> On Thu, Nov 9, 2017 at 5:

Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-14 Thread Ville Syrjälä
On Mon, Nov 13, 2017 at 01:47:26PM -0800, Lucas De Marchi wrote: > Hi Ville, > > On Thu, Nov 9, 2017 at 8:58 AM, Ville Syrjälä > wrote: > > On Thu, Nov 09, 2017 at 08:02:40AM -0800, Lucas De Marchi wrote: > >> On Thu, Nov 9, 2017 at 5:11 AM, Ville Syrjälä > >> wrote: > >> > On Thu, Nov 09, 2017

Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-13 Thread Lucas De Marchi
Hi Ville, On Thu, Nov 9, 2017 at 8:58 AM, Ville Syrjälä wrote: > On Thu, Nov 09, 2017 at 08:02:40AM -0800, Lucas De Marchi wrote: >> On Thu, Nov 9, 2017 at 5:11 AM, Ville Syrjälä >> wrote: >> > On Thu, Nov 09, 2017 at 02:58:04AM -0800, Lucas De Marchi wrote: >> >> Wa Display #1183 was recently a

Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-09 Thread Ville Syrjälä
On Thu, Nov 09, 2017 at 08:02:40AM -0800, Lucas De Marchi wrote: > On Thu, Nov 9, 2017 at 5:11 AM, Ville Syrjälä > wrote: > > On Thu, Nov 09, 2017 at 02:58:04AM -0800, Lucas De Marchi wrote: > >> Wa Display #1183 was recently added to workaround > >> "Failures when enabling DPLL0 with eDP link rat

Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-09 Thread Lucas De Marchi
On Thu, Nov 9, 2017 at 5:11 AM, Ville Syrjälä wrote: > On Thu, Nov 09, 2017 at 02:58:04AM -0800, Lucas De Marchi wrote: >> Wa Display #1183 was recently added to workaround >> "Failures when enabling DPLL0 with eDP link rate 2.16 >> or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz >> (CDCLK

Re: [Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-09 Thread Ville Syrjälä
On Thu, Nov 09, 2017 at 02:58:04AM -0800, Lucas De Marchi wrote: > Wa Display #1183 was recently added to workaround > "Failures when enabling DPLL0 with eDP link rate 2.16 > or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz > (CDCLK_CTL CD Frequency Select 10b or 11b) used in this > enablin

[Intel-gfx] [PATCH v3] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

2017-11-09 Thread Lucas De Marchi
Wa Display #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." This Workaround was designed to minimize the i