Re: [Intel-gfx] [PATCH v3 0/2] CNL port refactoring

2018-03-14 Thread Rodrigo Vivi
On Wed, Mar 14, 2018 at 01:36:51PM +0530, Mahesh Kumar wrote: > This series fixes CNL PORT_TX_DW5/7_LNO_D register address. > This series also introduces macros to get register address of > CNL_PORT_TX registers instead of defining for each DW instance. > > changes since V1: > completely kill

[Intel-gfx] [PATCH v3 0/2] CNL port refactoring

2018-03-14 Thread Mahesh Kumar
This series fixes CNL PORT_TX_DW5/7_LNO_D register address. This series also introduces macros to get register address of CNL_PORT_TX registers instead of defining for each DW instance. changes since V1: completely kill _MMIO_PORT6 macro changes since V2: use underscore prefix in macro merge

[Intel-gfx] [PATCH v3 0/2] CNL port refactoring

2018-03-12 Thread Mahesh Kumar
This series fixes CNL PORT_TX_DW5/7_LNO_D register address. This series also introduces macros to get register address of CNL_PORT_TX registers instead of defining for each DW instance. changes since V1: completely kill _MMIO_PORT6 macro changes since V2: use underscore prefix in macro merge