Re: [Intel-gfx] [PATCH v3 07/14] drm/i915/dp: cache common rates with sink rates

Reviewed-by: Manasi On Tue, Mar 28, 2017 at 05:59:07PM +0300, Jani Nikula wrote: > Now that source rates are static and sink rates are updated whenever > DPCD is updated, we can do and cache the intersection of them whenever > sink rates are updated. This reduces code

[Intel-gfx] [PATCH v3 07/14] drm/i915/dp: cache common rates with sink rates

Now that source rates are static and sink rates are updated whenever DPCD is updated, we can do and cache the intersection of them whenever sink rates are updated. This reduces code complexity, as we don't have to keep calling the functions to intersect. We also get rid of several common rates