At Fri, 4 Jul 2014 10:00:37 +0800,
mengdong@intel.com wrote:
From: Jani Nikula jani.nik...@intel.com
For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency
From: Jani Nikula jani.nik...@intel.com
For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So
