subject:"\[Intel\-gfx\] \[PATCH v3 4\/8\] drm\/i915\/mtl\: Add Support for C10 PHY message bus and pll programming"

Re: [Intel-gfx] [PATCH v3 4/8] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming

2023-04-06 Thread Imre Deak

On Thu, Apr 06, 2023 at 04:02:17PM +0300, Mika Kahola wrote: > From: Radhakrishna Sripada > > XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy > has a dedicated PIPE 5.2 Message bus for configuration. This message > bus is used to configure the phy internal registers. > >

[Intel-gfx] [PATCH v3 4/8] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming

2023-04-06 Thread Mika Kahola

From: Radhakrishna Sripada XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy has a dedicated PIPE 5.2 Message bus for configuration. This message bus is used to configure the phy internal registers. XELPDP has C10 phys to drive output to the EDP and the native output from