> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 8, 2023 7:42 PM
> To: Ville Syrjälä ; Kahola, Mika
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4] drm/i915/display: Support PSR entry VSC
> packet to be trans
On Wed, 08 Nov 2023, Ville Syrjälä wrote:
> On Wed, Nov 08, 2023 at 06:59:18PM +0200, Ville Syrjälä wrote:
>> On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
>> > Display driver shall read DPCD 00071h[3:1] during configuration
>> > to get PSR setup time. This register provides the
On Wed, Nov 08, 2023 at 06:59:18PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
> > Display driver shall read DPCD 00071h[3:1] during configuration
> > to get PSR setup time. This register provides the setup time
> > requirement on the VSC SDP entry
On Mon, Nov 06, 2023 at 01:42:28PM +0200, Mika Kahola wrote:
> Display driver shall read DPCD 00071h[3:1] during configuration
> to get PSR setup time. This register provides the setup time
> requirement on the VSC SDP entry packet. If setup time cannot be
> met with the current timings
> (e.g.,
On Mon, 2023-11-06 at 13:42 +0200, Mika Kahola wrote:
> Display driver shall read DPCD 00071h[3:1] during configuration
> to get PSR setup time. This register provides the setup time
> requirement on the VSC SDP entry packet. If setup time cannot be
> met with the current timings
> (e.g., PSR
Display driver shall read DPCD 00071h[3:1] during configuration
to get PSR setup time. This register provides the setup time
requirement on the VSC SDP entry packet. If setup time cannot be
met with the current timings
(e.g., PSR setup time + other blanking requirements > blanking time),
driver
