Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-07 Thread Jim Bride
On Fri, Aug 04, 2017 at 06:38:02PM +, Pandiyan, Dhinakaran wrote: > > > > On Thu, 2017-08-03 at 11:07 -0700, Rodrigo Vivi wrote: > > On Tue, Jul 18, 2017 at 2:34 PM, Jim Bride > > wrote: > > > According to the eDP spec, when the count field in TEST_SINK_MISC > >

Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-04 Thread Pandiyan, Dhinakaran
On Thu, 2017-08-03 at 11:07 -0700, Rodrigo Vivi wrote: > On Tue, Jul 18, 2017 at 2:34 PM, Jim Bride wrote: > > According to the eDP spec, when the count field in TEST_SINK_MISC > > increments then the six bytes of sink CRC information in the DPCD > > should be valid.

Re: [Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-03 Thread Rodrigo Vivi
On Tue, Jul 18, 2017 at 2:34 PM, Jim Bride wrote: > According to the eDP spec, when the count field in TEST_SINK_MISC > increments then the six bytes of sink CRC information in the DPCD > should be valid. Unfortunately, this doesn't seem to be the case > on some

[Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Account for sink CRC raciness on some panels

2017-07-18 Thread Jim Bride
According to the eDP spec, when the count field in TEST_SINK_MISC increments then the six bytes of sink CRC information in the DPCD should be valid. Unfortunately, this doesn't seem to be the case on some panels, and as a result we get some incorrect and inconsistent values from the sink CRC DPCD