Re: [Intel-gfx] [PATCH v5 09/22] drm/i915/mtl: C20 HW readout

2023-03-27 Thread Imre Deak
On Thu, Mar 16, 2023 at 01:13:22PM +0200, Mika Kahola wrote: > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates. > The PLL settings are based on table, not for algorithmic alternative. > For DP 1.4 only MPLLB is in use. > > Once register settings are done, we read back C20 HW state. > >

Re: [Intel-gfx] [PATCH v5 09/22] drm/i915/mtl: C20 HW readout

2023-03-24 Thread Gustavo Sousa
On Thu, Mar 16, 2023 at 01:13:22PM +0200, Mika Kahola wrote: > Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates. > The PLL settings are based on table, not for algorithmic alternative. > For DP 1.4 only MPLLB is in use. > > Once register settings are done, we read back C20 HW state. > >

[Intel-gfx] [PATCH v5 09/22] drm/i915/mtl: C20 HW readout

2023-03-16 Thread Mika Kahola
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates. The PLL settings are based on table, not for algorithmic alternative. For DP 1.4 only MPLLB is in use. Once register settings are done, we read back C20 HW state. BSpec: 64568 v2: Update rbr, hbr1, hbr2, and hbr3 pll configurations 4 and 5