Re: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

2019-09-11 Thread Anshuman Gupta 
On 2019-09-11 at 11:21:42 +0300, Imre Deak wrote:
> On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> > Hi Imre,
> > Thanks for reviewing the pacthes i will rework the patches.
> > There are few comments from my side which will help to rework. 
> > > > Add max_dc_state and tgl_set_target_dc_state() API
> > > > in order to enable DC3CO state with existing DC states.
> > > > max_dc_state will enable/disable the desired DC state in
> > > > DC_STATE_EN reg when "DC Off" power well gets disable/enable.
> > > > 
> > > > v2: commit log improvement.
> > > > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > > > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > > > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > > > to a appropriate place haswell_crtc_enable(). [Imre]
> > > > Changed the DC3CO power well enabled call back logic as
> > > > recommended in review comments. [Imre]
> > > > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > > > v5: using udelay() instead of waiting for DC3CO exit status.
> > > > v6: Fixed minor unwanted change.
> > > > v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
> > > > 
> > > > Cc: Jani Nikula 
> > > > Cc: Imre Deak 
> > > > Cc: Animesh Manna 
> > > > Signed-off-by: Anshuman Gupta 
> > > > ---
> > > >  .../drm/i915/display/intel_display_power.c| 111 ++
> > > >  .../drm/i915/display/intel_display_power.h|   3 +
> > > >  drivers/gpu/drm/i915/i915_drv.h   |   1 +
> > > >  3 files changed, 95 insertions(+), 20 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 496fa1b53ffb..83b10f61ee42 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct 
> > > > drm_i915_private *dev_priv, u32 state)
> > > > dev_priv->csr.dc_state = val & mask;
> > > >  }
> > > >  
> > > > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > > 
> > > Should be tgl_enable_dc3co(), to match the rest of DC state helpers.
> > > 
> > > > +{
> > > > +   if (!dev_priv->psr.sink_psr2_support)
> > > > +   return;
> > > 
> > > PSR knows when to enable DC3co, so no need to double-check that here.
> > > 
> > > > +
> > > > +   if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> > > 
> > > This check is out-of-place wrt. the same checks for other DC states.
> > > 
> > > > +   gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > > +}
> > > > +
> > > > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > > > +{
> > > > +   u32 val;
> > > > +
> > > > +   val = I915_READ(DC_STATE_EN);
> > > > +   val &= ~DC_STATE_DC3CO_STATUS;
> > > > +   I915_WRITE(DC_STATE_EN, val);
> > > > +   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > +   /*
> > > > +* Delay of 200us DC3CO Exit time B.Spec 49196
> > > > +*/
> > > > +   udelay(200);
> > > > +}
> > > > +
> > > >  static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > > >  {
> > > > assert_can_enable_dc9(dev_priv);
> > > > @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct 
> > > > drm_i915_private *dev_priv)
> > > >  static bool gen9_dc_off_power_well_enabled(struct drm_i915_private 
> > > > *dev_priv,
> > > >struct i915_power_well 
> > > > *power_well)
> > > >  {
> > > > -   return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) 
> > > > == 0;
> > > > +   return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> > > > +   (I915_READ(DC_STATE_EN) & 
> > > > DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> > > >  }
> > > >  
> > > >  static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> > > > @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct 
> > > > drm_i915_private *dev_priv)
> > > >  {
> > > > struct intel_cdclk_state cdclk_state = {};
> > > >  
> > > > -   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > > +   if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
> > > > +   tgl_disallow_dc3co(dev_priv);
> > > > +   } else {
> > > 
> > > With an early return you can avoid the extra diff and make reviewing
> > > easier.
> > > 
> > > > +   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > >  
> > > > -   dev_priv->display.get_cdclk(dev_priv, _state);
> > > > -   /* Can't read out voltage_level so can't use 
> > > > intel_cdclk_changed() */
> > > > -   WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, 
> > > > _state));
> > > > +

Re: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

2019-09-11 Thread Imre Deak 
On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> Hi Imre,
> Thanks for reviewing the pacthes i will rework the patches.
> There are few comments from my side which will help to rework. 
> > > Add max_dc_state and tgl_set_target_dc_state() API
> > > in order to enable DC3CO state with existing DC states.
> > > max_dc_state will enable/disable the desired DC state in
> > > DC_STATE_EN reg when "DC Off" power well gets disable/enable.
> > > 
> > > v2: commit log improvement.
> > > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > > to a appropriate place haswell_crtc_enable(). [Imre]
> > > Changed the DC3CO power well enabled call back logic as
> > > recommended in review comments. [Imre]
> > > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > > v5: using udelay() instead of waiting for DC3CO exit status.
> > > v6: Fixed minor unwanted change.
> > > v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
> > > 
> > > Cc: Jani Nikula 
> > > Cc: Imre Deak 
> > > Cc: Animesh Manna 
> > > Signed-off-by: Anshuman Gupta 
> > > ---
> > >  .../drm/i915/display/intel_display_power.c| 111 ++
> > >  .../drm/i915/display/intel_display_power.h|   3 +
> > >  drivers/gpu/drm/i915/i915_drv.h   |   1 +
> > >  3 files changed, 95 insertions(+), 20 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 496fa1b53ffb..83b10f61ee42 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct 
> > > drm_i915_private *dev_priv, u32 state)
> > >   dev_priv->csr.dc_state = val & mask;
> > >  }
> > >  
> > > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> > 
> > Should be tgl_enable_dc3co(), to match the rest of DC state helpers.
> > 
> > > +{
> > > + if (!dev_priv->psr.sink_psr2_support)
> > > + return;
> > 
> > PSR knows when to enable DC3co, so no need to double-check that here.
> > 
> > > +
> > > + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> > 
> > This check is out-of-place wrt. the same checks for other DC states.
> > 
> > > + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > > +}
> > > +
> > > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > > +{
> > > + u32 val;
> > > +
> > > + val = I915_READ(DC_STATE_EN);
> > > + val &= ~DC_STATE_DC3CO_STATUS;
> > > + I915_WRITE(DC_STATE_EN, val);
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > + /*
> > > +  * Delay of 200us DC3CO Exit time B.Spec 49196
> > > +  */
> > > + udelay(200);
> > > +}
> > > +
> > >  static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> > >  {
> > >   assert_can_enable_dc9(dev_priv);
> > > @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct 
> > > drm_i915_private *dev_priv)
> > >  static bool gen9_dc_off_power_well_enabled(struct drm_i915_private 
> > > *dev_priv,
> > >  struct i915_power_well *power_well)
> > >  {
> > > - return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > > + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> > > + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> > >  }
> > >  
> > >  static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> > > @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct 
> > > drm_i915_private *dev_priv)
> > >  {
> > >   struct intel_cdclk_state cdclk_state = {};
> > >  
> > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > + if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
> > > + tgl_disallow_dc3co(dev_priv);
> > > + } else {
> > 
> > With an early return you can avoid the extra diff and make reviewing
> > easier.
> > 
> > > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >  
> > > - dev_priv->display.get_cdclk(dev_priv, _state);
> > > - /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> > > - WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, _state));
> > > + dev_priv->display.get_cdclk(dev_priv, _state);
> > > + /*
> > > +  * Can't read out voltage_level so can't use
> > > +  * intel_cdclk_changed()
> > > +  */
> > > + WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw,
> > > +   _state));
> > >  
> > > - gen9_assert_dbuf_enabled(dev_priv);
> > > + gen9_assert_dbuf_enabled(dev_priv);
> > >  
> > > - if (IS_GEN9_LP(dev_priv))
> > > -

Re: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

2019-09-09 Thread Anshuman Gupta 
On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
Hi Imre,
Thanks for reviewing the pacthes i will rework the patches.
There are few comments from my side which will help to rework. 
> > Add max_dc_state and tgl_set_target_dc_state() API
> > in order to enable DC3CO state with existing DC states.
> > max_dc_state will enable/disable the desired DC state in
> > DC_STATE_EN reg when "DC Off" power well gets disable/enable.
> > 
> > v2: commit log improvement.
> > v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> > Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> > Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> > to a appropriate place haswell_crtc_enable(). [Imre]
> > Changed the DC3CO power well enabled call back logic as
> > recommended in review comments. [Imre]
> > v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> > v5: using udelay() instead of waiting for DC3CO exit status.
> > v6: Fixed minor unwanted change.
> > v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
> > 
> > Cc: Jani Nikula 
> > Cc: Imre Deak 
> > Cc: Animesh Manna 
> > Signed-off-by: Anshuman Gupta 
> > ---
> >  .../drm/i915/display/intel_display_power.c| 111 ++
> >  .../drm/i915/display/intel_display_power.h|   3 +
> >  drivers/gpu/drm/i915/i915_drv.h   |   1 +
> >  3 files changed, 95 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 496fa1b53ffb..83b10f61ee42 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct drm_i915_private 
> > *dev_priv, u32 state)
> > dev_priv->csr.dc_state = val & mask;
> >  }
> >  
> > +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
> 
> Should be tgl_enable_dc3co(), to match the rest of DC state helpers.
> 
> > +{
> > +   if (!dev_priv->psr.sink_psr2_support)
> > +   return;
> 
> PSR knows when to enable DC3co, so no need to double-check that here.
> 
> > +
> > +   if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
> 
> This check is out-of-place wrt. the same checks for other DC states.
> 
> > +   gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> > +}
> > +
> > +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> > +{
> > +   u32 val;
> > +
> > +   val = I915_READ(DC_STATE_EN);
> > +   val &= ~DC_STATE_DC3CO_STATUS;
> > +   I915_WRITE(DC_STATE_EN, val);
> > +   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +   /*
> > +* Delay of 200us DC3CO Exit time B.Spec 49196
> > +*/
> > +   udelay(200);
> > +}
> > +
> >  static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> >  {
> > assert_can_enable_dc9(dev_priv);
> > @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct 
> > drm_i915_private *dev_priv)
> >  static bool gen9_dc_off_power_well_enabled(struct drm_i915_private 
> > *dev_priv,
> >struct i915_power_well *power_well)
> >  {
> > -   return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > +   return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> > +   (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> >  }
> >  
> >  static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> > @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct 
> > drm_i915_private *dev_priv)
> >  {
> > struct intel_cdclk_state cdclk_state = {};
> >  
> > -   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +   if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
> > +   tgl_disallow_dc3co(dev_priv);
> > +   } else {
> 
> With an early return you can avoid the extra diff and make reviewing
> easier.
> 
> > +   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> > -   dev_priv->display.get_cdclk(dev_priv, _state);
> > -   /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> > -   WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, _state));
> > +   dev_priv->display.get_cdclk(dev_priv, _state);
> > +   /*
> > +* Can't read out voltage_level so can't use
> > +* intel_cdclk_changed()
> > +*/
> > +   WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw,
> > + _state));
> >  
> > -   gen9_assert_dbuf_enabled(dev_priv);
> > +   gen9_assert_dbuf_enabled(dev_priv);
> >  
> > -   if (IS_GEN9_LP(dev_priv))
> > -   bxt_verify_ddi_phy_power_wells(dev_priv);
> > +   if (IS_GEN9_LP(dev_priv))
> > +   bxt_verify_ddi_phy_power_wells(dev_priv);
> >  
> > -   if (INTEL_GEN(dev_priv) >= 11)
> > -   /*
> > -

Re: [Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

2019-09-08 Thread Imre Deak 
On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> Add max_dc_state and tgl_set_target_dc_state() API
> in order to enable DC3CO state with existing DC states.
> max_dc_state will enable/disable the desired DC state in
> DC_STATE_EN reg when "DC Off" power well gets disable/enable.
> 
> v2: commit log improvement.
> v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
> Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
> Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
> to a appropriate place haswell_crtc_enable(). [Imre]
> Changed the DC3CO power well enabled call back logic as
> recommended in review comments. [Imre]
> v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
> v5: using udelay() instead of waiting for DC3CO exit status.
> v6: Fixed minor unwanted change.
> v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
> 
> Cc: Jani Nikula 
> Cc: Imre Deak 
> Cc: Animesh Manna 
> Signed-off-by: Anshuman Gupta 
> ---
>  .../drm/i915/display/intel_display_power.c| 111 ++
>  .../drm/i915/display/intel_display_power.h|   3 +
>  drivers/gpu/drm/i915/i915_drv.h   |   1 +
>  3 files changed, 95 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 496fa1b53ffb..83b10f61ee42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct drm_i915_private 
> *dev_priv, u32 state)
>   dev_priv->csr.dc_state = val & mask;
>  }
>  
> +static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)

Should be tgl_enable_dc3co(), to match the rest of DC state helpers.

> +{
> + if (!dev_priv->psr.sink_psr2_support)
> + return;

PSR knows when to enable DC3co, so no need to double-check that here.

> +
> + if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)

This check is out-of-place wrt. the same checks for other DC states.

> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> +}
> +
> +static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = I915_READ(DC_STATE_EN);
> + val &= ~DC_STATE_DC3CO_STATUS;
> + I915_WRITE(DC_STATE_EN, val);
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + /*
> +  * Delay of 200us DC3CO Exit time B.Spec 49196
> +  */
> + udelay(200);
> +}
> +
>  static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
>  {
>   assert_can_enable_dc9(dev_priv);
> @@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct 
> drm_i915_private *dev_priv)
>  static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
>  struct i915_power_well *power_well)
>  {
> - return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> + return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
> + (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
>  }
>  
>  static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> @@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct 
> drm_i915_private *dev_priv)
>  {
>   struct intel_cdclk_state cdclk_state = {};
>  
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
> + tgl_disallow_dc3co(dev_priv);
> + } else {

With an early return you can avoid the extra diff and make reviewing
easier.

> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> - dev_priv->display.get_cdclk(dev_priv, _state);
> - /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> - WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, _state));
> + dev_priv->display.get_cdclk(dev_priv, _state);
> + /*
> +  * Can't read out voltage_level so can't use
> +  * intel_cdclk_changed()
> +  */
> + WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw,
> +   _state));
>  
> - gen9_assert_dbuf_enabled(dev_priv);
> + gen9_assert_dbuf_enabled(dev_priv);
>  
> - if (IS_GEN9_LP(dev_priv))
> - bxt_verify_ddi_phy_power_wells(dev_priv);
> + if (IS_GEN9_LP(dev_priv))
> + bxt_verify_ddi_phy_power_wells(dev_priv);
>  
> - if (INTEL_GEN(dev_priv) >= 11)
> - /*
> -  * DMC retains HW context only for port A, the other combo
> -  * PHY's HW context for port B is lost after DC transitions,
> -  * so we need to restore it manually.
> -  */
> - intel_combo_phy_init(dev_priv);
> + if (INTEL_GEN(dev_priv) >= 11)
> + /*
> +

[Intel-gfx] [PATCH v7 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

2019-09-07 Thread Anshuman Gupta 
Add max_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
max_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.

v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.

Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Animesh Manna 
Signed-off-by: Anshuman Gupta 
---
 .../drm/i915/display/intel_display_power.c| 111 ++
 .../drm/i915/display/intel_display_power.h|   3 +
 drivers/gpu/drm/i915/i915_drv.h   |   1 +
 3 files changed, 95 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 496fa1b53ffb..83b10f61ee42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -772,6 +772,29 @@ static void gen9_set_dc_state(struct drm_i915_private 
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
 }
 
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+   if (!dev_priv->psr.sink_psr2_support)
+   return;
+
+   if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+   gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   val = I915_READ(DC_STATE_EN);
+   val &= ~DC_STATE_DC3CO_STATUS;
+   I915_WRITE(DC_STATE_EN, val);
+   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+   /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+   udelay(200);
+}
+
 static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
assert_can_enable_dc9(dev_priv);
@@ -939,7 +962,8 @@ static void bxt_verify_ddi_phy_power_wells(struct 
drm_i915_private *dev_priv)
 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
-   return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+   return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+   (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -955,24 +979,32 @@ static void gen9_disable_dc_states(struct 
drm_i915_private *dev_priv)
 {
struct intel_cdclk_state cdclk_state = {};
 
-   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+   if (dev_priv->csr.max_dc_state & DC_STATE_EN_DC3CO) {
+   tgl_disallow_dc3co(dev_priv);
+   } else {
+   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-   dev_priv->display.get_cdclk(dev_priv, _state);
-   /* Can't read out voltage_level so can't use intel_cdclk_changed() */
-   WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw, _state));
+   dev_priv->display.get_cdclk(dev_priv, _state);
+   /*
+* Can't read out voltage_level so can't use
+* intel_cdclk_changed()
+*/
+   WARN_ON(intel_cdclk_needs_modeset(_priv->cdclk.hw,
+ _state));
 
-   gen9_assert_dbuf_enabled(dev_priv);
+   gen9_assert_dbuf_enabled(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv))
-   bxt_verify_ddi_phy_power_wells(dev_priv);
+   if (IS_GEN9_LP(dev_priv))
+   bxt_verify_ddi_phy_power_wells(dev_priv);
 
-   if (INTEL_GEN(dev_priv) >= 11)
-   /*
-* DMC retains HW context only for port A, the other combo
-* PHY's HW context for port B is lost after DC transitions,
-* so we need to restore it manually.
-*/
-   intel_combo_phy_init(dev_priv);
+   if (INTEL_GEN(dev_priv) >= 11)
+   /*
+* DMC retains HW context only for port A, the other
+* combo PHY's HW context for port B is lost after
+* DC transitions, so we need to restore it manually.
+*/
+   intel_combo_phy_init(dev_priv);
+   }
 }
 
 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
@@ -987,10 +1019,48 @@ static void gen9_dc_off_power_well_disable(struct