On Thu, 28 Mar 2024, Imre Deak wrote:
> On Wed, Mar 20, 2024 at 10:11:41PM +0200, Imre Deak wrote:
>> Fix the calculation of the DSC line buffer depth. This is limited both
>> by the source's and sink's maximum line buffer depth, but the former one
>> was not taken into account. On all Intel
On Wed, Mar 20, 2024 at 10:11:41PM +0200, Imre Deak wrote:
> Fix the calculation of the DSC line buffer depth. This is limited both
> by the source's and sink's maximum line buffer depth, but the former one
> was not taken into account. On all Intel platform's the source's maximum
> buffer depth
On Tue, Mar 26, 2024 at 12:50:17PM -0700, Manasi Navare wrote:
Hi,
> Hi Imre,
>
> Thanks for the DSC fixes.
>
> Would the line buf depth calculation that was getting set to 0 impact
> DSC on all platforms or was this issue only specific to MTL and was
> getting set correctly with older
Hi Imre,
Thanks for the DSC fixes.
Would the line buf depth calculation that was getting set to 0 impact
DSC on all platforms
or was this issue only specific to MTL and was getting set correctly
with older platforms?
We didnt notice any DSC issues/corruptions with ADL based systems.
The actual
On 3/21/2024 1:41 AM, Imre Deak wrote:
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall limit is simply the minimum of the
