Re: [PATCH 06/14] drm/i915/dpio: Rename some variables
On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use a constent 'tmp' as the variable name for the register
*consistent
> values during rmw when we don't deal with multiple registers
> in parallel.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++
> 1 file changed, 48 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 01f800b6b30e..0a738b491c40 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state
> *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> const struct i9xx_dpll_hw_state *hw_state =
> _state->dpll_hw_state.i9xx;
> - struct dpll clock;
> - u32 mdiv;
> int refclk = 10;
> + struct dpll clock;
> + u32 tmp;
>
> /* In case of DSI, DPLL will not be used */
> if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
> return;
>
> vlv_dpio_get(dev_priv);
> - mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> vlv_dpio_put(dev_priv);
>
> - clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
> - clock.m2 = mdiv & DPIO_M2DIV_MASK;
> - clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
> - clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
> - clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
> + clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
> + clock.m2 = tmp & DPIO_M2DIV_MASK;
> + clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
> + clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
> + clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
>
> crtc_state->port_clock = vlv_calc_dpll_params(refclk, );
> }
> @@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state
> *crtc_state)
> static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>enum dpio_phy phy)
> {
> - u32 reg_val;
> + u32 tmp;
>
> /*
>* PLLB opamp always calibrates to max value of 0x3f, force enable it
>* and set it to a reasonable value instead.
>*/
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> - reg_val &= 0xff00;
> - reg_val |= 0x0030;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp &= 0xff00;
> + tmp |= 0x0030;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> - reg_val &= 0x00ff;
> - reg_val |= 0x8c00;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> + tmp &= 0x00ff;
> + tmp |= 0x8c00;
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> - reg_val &= 0xff00;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> + tmp &= 0xff00;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> - reg_val &= 0x00ff;
> - reg_val |= 0xb000;
> - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> + tmp &= 0x00ff;
> + tmp |= 0xb000;
> + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
> }
>
> static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
> @@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct
> intel_crtc_state *crtc_state)
> const struct dpll *clock = _state->dpll;
> enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> enum pipe pipe = crtc->pipe;
> - u32 mdiv, coreclk, reg_val;
> + u32 tmp, coreclk;
>
> vlv_dpio_get(dev_priv);
>
> @@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct
> intel_crtc_state *crtc_state)
> vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
>
> /* Disable target IRef on PLL */
> - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> - reg_val &= 0x00ff;
> - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
> + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> + tmp &= 0x00ff;
> + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
>
> /* Disable fast lock */
> vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
>
> /* Set idtafcrecal before PLL is enabled */
> - mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
> + tmp = (clock->m1 <<
[PATCH 06/14] drm/i915/dpio: Rename some variables
From: Ville Syrjälä
Use a constent 'tmp' as the variable name for the register
values during rmw when we don't deal with multiple registers
in parallel.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++
1 file changed, 48 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 01f800b6b30e..0a738b491c40 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state
*crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
const struct i9xx_dpll_hw_state *hw_state =
_state->dpll_hw_state.i9xx;
- struct dpll clock;
- u32 mdiv;
int refclk = 10;
+ struct dpll clock;
+ u32 tmp;
/* In case of DSI, DPLL will not be used */
if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
return;
vlv_dpio_get(dev_priv);
- mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
vlv_dpio_put(dev_priv);
- clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
- clock.m2 = mdiv & DPIO_M2DIV_MASK;
- clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
- clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
- clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+ clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
+ clock.m2 = tmp & DPIO_M2DIV_MASK;
+ clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
+ clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
+ clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
crtc_state->port_clock = vlv_calc_dpll_params(refclk, );
}
@@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state
*crtc_state)
static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- u32 reg_val;
+ u32 tmp;
/*
* PLLB opamp always calibrates to max value of 0x3f, force enable it
* and set it to a reasonable value instead.
*/
- reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
- reg_val &= 0xff00;
- reg_val |= 0x0030;
- vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+ tmp &= 0xff00;
+ tmp |= 0x0030;
+ vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
- reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
- reg_val &= 0x00ff;
- reg_val |= 0x8c00;
- vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+ tmp &= 0x00ff;
+ tmp |= 0x8c00;
+ vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
- reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
- reg_val &= 0xff00;
- vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+ tmp &= 0xff00;
+ vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
- reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
- reg_val &= 0x00ff;
- reg_val |= 0xb000;
- vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+ tmp &= 0x00ff;
+ tmp |= 0xb000;
+ vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
}
static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state
*crtc_state)
const struct dpll *clock = _state->dpll;
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
enum pipe pipe = crtc->pipe;
- u32 mdiv, coreclk, reg_val;
+ u32 tmp, coreclk;
vlv_dpio_get(dev_priv);
@@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct
intel_crtc_state *crtc_state)
vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x010f);
/* Disable target IRef on PLL */
- reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
- reg_val &= 0x00ff;
- vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
+ tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
+ tmp &= 0x00ff;
+ vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
/* Disable fast lock */
vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
/* Set idtafcrecal before PLL is enabled */
- mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+ tmp = (clock->m1 << DPIO_M1DIV_SHIFT) |
(clock->m2 & DPIO_M2DIV_MASK) |
(clock->p1 << DPIO_P1_SHIFT) |
(clock->p2 << DPIO_P2_SHIFT) |
@@ -1936,11 +1936,11
