subject:"\[PATCH 07\/14\] drm\/i915\/dpio\: s\/port\/ch\/"

Re: [PATCH 07/14] drm/i915/dpio: s/port/ch/

2024-04-22 Thread Jani Nikula

On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Stop calling the DPIO PHY channel "port". Just say "ch", which
> is already used in a bunch of places.
>
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++
>  drivers/gpu/drm/i915/display/intel_dpll.c | 54 +--
>  2 files changed, 49 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 6cbee88e608f..e4a04c9b5b19 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder 
> *encoder,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
>uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
>  
>   if (tx3_demph)
> - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
> + vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x0003);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
> *encoder,
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>   /* Program Tx lane resets to default */
>   vlv_dpio_get(dev_priv);
>  
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
>DPIO_PCS_TX_LANE2_RESET |
>DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
>DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
>DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
>(1  
>   /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x1500);
> - vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x4040);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x1500);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x4040);
>  
>   vlv_dpio_put(dev_priv);
>  }
> @@ -1126,7 +1126,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>   enum pipe pipe = crtc->pipe;
>   enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>   u32 val;
> @@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder,
>   else
>   val &= ~(1<<21);
>   val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
> + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
>  
>   /* Program lane clock */
> -

[PATCH 07/14] drm/i915/dpio: s/port/ch/

2024-04-22 Thread Ville Syrjala

From: Ville Syrjälä 

Stop calling the DPIO PHY channel "port". Just say "ch", which
is already used in a bunch of places.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++
 drivers/gpu/drm/i915/display/intel_dpll.c | 54 +--
 2 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 6cbee88e608f..e4a04c9b5b19 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 uniqtranscale_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
 
if (tx3_demph)
-   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
+   vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x0003);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
-   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x0003);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
+   vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
 
vlv_dpio_put(dev_priv);
 }
@@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder 
*encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
/* Program Tx lane resets to default */
vlv_dpio_get(dev_priv);
 
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 DPIO_PCS_TX_LANE2_RESET |
 DPIO_PCS_TX_LANE1_RESET);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
 (1uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum pipe pipe = crtc->pipe;
enum dpio_phy phy = vlv_pipe_to_phy(pipe);
u32 val;
@@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder 
*encoder,
else
val &= ~(1<<21);
val |= 0x001000c4;
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
 
/* Program lane clock */
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
+   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
 
vlv_dpio_put(dev_priv);
 }
@@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-   enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+   enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
vlv_dpio_get(dev_priv);
-   vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x);
-

Re: [PATCH 07/14] drm/i915/dpio: s/port/ch/

[PATCH 07/14] drm/i915/dpio: s/port/ch/

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