On Mon, 22 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DPIO PHY registers follow clear numbering rules. Express
> those in a few macros to get rid of the hand calculated
> final offsets.
>
> Signed-off-by: Ville Syrjälä
Okay, this one was even worse than patch 13. I admit I didn't go through
everything, but this is not just rubber stamping either, as I did set up
a spreadsheet to verify a lot of the changes here. Did a few spot checks
on some of the other stuff, and didn't find any mishaps.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 271 +++---
> 2 files changed, 99 insertions(+), 174 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 89a51b420075..fa665d353df9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1078,7 +1078,7 @@ void vlv_set_phy_signal_level(struct intel_encoder
> *encoder,
> vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
>
> if (tx3_demph)
> - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
> + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
>
> vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x0003);
> vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b24ce3cff1a0..6d16f9944eff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -195,10 +195,22 @@
> #define DPIO_SFR_BYPASS (1 << 1)
> #define DPIO_CMNRST (1 << 0)
>
> +#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 +
> (dw) * 4)
> +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw)
> * 4)
> +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> +
> /*
> * Per pipe/PLL DPIO regs
> */
> -#define _VLV_PLL_DW3_CH0 0x800c
> +#define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3)
> #define DPIO_POST_DIV_SHIFT(28) /* 3 bits */
> #define DPIO_POST_DIV_DAC 0
> #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
> @@ -211,10 +223,8 @@
> #define DPIO_ENABLE_CALIBRATION(1 << 11)
> #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
> #define DPIO_M2DIV_MASK0xff
> -#define _VLV_PLL_DW3_CH1 0x802c
> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>
> -#define _VLV_PLL_DW5_CH0 0x8014
> +#define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5)
> #define DPIO_REFSEL_OVERRIDE 27
> #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
> #define DPIO_BIAS_CURRENT_CTL_SHIFT21 /* 3 bits, always 0x7 */
> @@ -222,101 +232,60 @@
> #define DPIO_PLL_REFCLK_SEL_MASK 3
> #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
> #define DPIO_CLK_BIAS_CTL_SHIFT8 /* always set to 0x5 */
> -#define _VLV_PLL_DW5_CH1 0x8034
> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>
> -#define _VLV_PLL_DW7_CH0 0x801c
> -#define _VLV_PLL_DW7_CH1 0x803c
> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
> +#define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7)
>
> -#define _VLV_PLL_DW16_CH00x8040
> -#define _VLV_PLL_DW16_CH10x8060
> -#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
> +#define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16)
>
> -#define _VLV_PLL_DW17_CH00x8044
> -#define _VLV_PLL_DW17_CH10x8064
> -#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
> +#define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17)
>
> -#define _VLV_PLL_DW18_CH00x8048
> -#define _VLV_PLL_DW18_CH10x8068
> -#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
> +#define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18)
>
> -#define _VLV_PLL_DW19_CH00x804c
> -#define _VLV_PLL_DW19_CH10x806c
> -#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
> +#define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19)
>
> -/*
