Re: [PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

2024-04-22 Thread Jani Nikula 
On Mon, 22 Apr 2024, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> Pull the VLV/CHV DPIO PHY sideband registers to their own file.
>
> Signed-off-by: Ville Syrjälä 

git show --color-moved tells me this is fine.

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   1 +
>  .../i915/display/intel_display_power_well.c   |   1 +
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
>  drivers/gpu/drm/i915/display/intel_dpll.c |   1 +
>  .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++
>  drivers/gpu/drm/i915/i915_reg.h   | 298 -
>  6 files changed, 313 insertions(+), 298 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 96ed1490fec7..59f989207c74 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -120,6 +120,7 @@
>  #include "skl_scaler.h"
>  #include "skl_universal_plane.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_dsi.h"
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e4ba6efc90e6..83f616097a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -27,6 +27,7 @@
>  #include "intel_tc.h"
>  #include "intel_vga.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  #include "vlv_sideband_reg.h"
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 11875d18a8fc..d20e4e9cf7f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -30,6 +30,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dpio_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index c2ee95993a96..a981f45facb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,7 @@
>  #include "intel_panel.h"
>  #include "intel_pps.h"
>  #include "intel_snps_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  struct intel_dpll_funcs {
> diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h 
> b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> new file mode 100644
> index ..477506f0b2cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> @@ -0,0 +1,309 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __VLV_DPIO_PHY_REGS_H__
> +#define __VLV_DPIO_PHY_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + 
> (dw) * 4)
> +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) 
> * 4)
> +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> +
> +/*
> + * Per pipe/PLL DPIO regs
> + */
> +#define VLV_PLL_DW3(ch)  _VLV_PLL((ch), 3)
> +#define   DPIO_S1_DIV_MASK   REG_GENMASK(30, 28)
> +#define   DPIO_S1_DIV(s1)REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
> +#define   DPIO_S1_DIV_DAC0 /* 10, DAC 25-225M rate */
> +#define   DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
> +#define   DPIO_S1_DIV_LVDS1  2 /* 14 */
> +#define   DPIO_S1_DIV_LVDS2  3 /* 7 */
> +#define   DPIO_K_DIV_MASKREG_GENMASK(27, 24)
> +#define   DPIO_K_DIV(k)  REG_FIELD_PREP(DPIO_K_DIV_MASK, 
> (k))
> +#define   DPIO_P1_DIV_MASK   REG_GENMASK(23, 21)
> +#define   DPIO_P1_DIV(p1)REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
> +#define   DPIO_P2_DIV_MASK   REG_GENMASK(20, 16)
> +#define   DPIO_P2_DIV(p2)REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
> +#define   DPIO_N_DIV_MASKREG_GENMASK(15, 12)
> +#define   DPIO_N_DIV(n)  REG_FIELD_PREP(DPIO_N_DIV_MASK, 
> (n))
> +#define   DPIO_ENABLE_CALIBRATIONREG_BIT(11)
> +#define   DPIO_M1_DIV_MASK

[PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

2024-04-22 Thread Ville Syrjala 
From: Ville Syrjälä 

Pull the VLV/CHV DPIO PHY sideband registers to their own file.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
 drivers/gpu/drm/i915/display/intel_dpll.c |   1 +
 .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++
 drivers/gpu/drm/i915/i915_reg.h   | 298 -
 6 files changed, 313 insertions(+), 298 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 96ed1490fec7..59f989207c74 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -120,6 +120,7 @@
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_pll.h"
 #include "vlv_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e4ba6efc90e6..83f616097a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -27,6 +27,7 @@
 #include "intel_tc.h"
 #include "intel_vga.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 #include "vlv_sideband_reg.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 11875d18a8fc..d20e4e9cf7f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -30,6 +30,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpio_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
b/drivers/gpu/drm/i915/display/intel_dpll.c
index c2ee95993a96..a981f45facb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,7 @@
 #include "intel_panel.h"
 #include "intel_pps.h"
 #include "intel_snps_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 struct intel_dpll_funcs {
diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h 
b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
new file mode 100644
index ..477506f0b2cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __VLV_DPIO_PHY_REGS_H__
+#define __VLV_DPIO_PHY_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
+#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
+#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
+#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
+#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
+#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + 
(dw) * 4)
+#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
+#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 
4)
+#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
+
+/*
+ * Per pipe/PLL DPIO regs
+ */
+#define VLV_PLL_DW3(ch)_VLV_PLL((ch), 3)
+#define   DPIO_S1_DIV_MASK REG_GENMASK(30, 28)
+#define   DPIO_S1_DIV(s1)  REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
+#define   DPIO_S1_DIV_DAC  0 /* 10, DAC 25-225M rate */
+#define   DPIO_S1_DIV_HDMIDP   1 /* 5, DAC 225-400M rate */
+#define   DPIO_S1_DIV_LVDS12 /* 14 */
+#define   DPIO_S1_DIV_LVDS23 /* 7 */
+#define   DPIO_K_DIV_MASK  REG_GENMASK(27, 24)
+#define   DPIO_K_DIV(k)REG_FIELD_PREP(DPIO_K_DIV_MASK, 
(k))
+#define   DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
+#define   DPIO_P1_DIV(p1)  REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
+#define   DPIO_P2_DIV_MASK REG_GENMASK(20, 16)
+#define   DPIO_P2_DIV(p2)  REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
+#define   DPIO_N_DIV_MASK  REG_GENMASK(15, 12)
+#define   DPIO_N_DIV(n)REG_FIELD_PREP(DPIO_N_DIV_MASK, 
(n))
+#define   DPIO_ENABLE_CALIBRATION  REG_BIT(11)
+#define   DPIO_M1_DIV_MASK REG_GENMASK(10, 8)
+#define   DPIO_M1_DIV(m1)  REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
+#define   DPIO_M2_DIV_MASK REG_GENMASK(7, 0)
+#define   DPIO_M2_DIV(m2)  REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
+
+#define VLV_PLL_DW5(ch)_VLV_PLL((ch), 5)
+#define