Re: [Intel-gfx] [PATCH] cpufreq: Add dummy cpufreq_cpu_get/put for CONFIG_CPU_FREQ=n

2013-10-17 Thread Daniel Vetter
On Thu, Oct 17, 2013 at 01:00:42AM +0200, Rafael J. Wysocki wrote: On Tuesday, October 08, 2013 10:56:11 AM Daniel Vetter wrote: The drm/i915 driver wants to adjust it's own power policies using the cpu policies as a guideline (we can implicitly boost the cpus through the gpus on some

Re: [Intel-gfx] [PATCH 2/2] [v2] drm/i915: Disable GGTT PTEs on GEN6+ suspend

2013-10-17 Thread Takashi Iwai
At Wed, 16 Oct 2013 18:27:33 +0100, Chris Wilson wrote: On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote: On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote: So clearing the valid bit should result in the GPU reporting errors for delayed accesses, but none were

[Intel-gfx] Target Display Mode for Linux

2013-10-17 Thread Chris Rydalch
Hello, I've been directed here from the Fedora developers list, looking for some answers regarding computers with bi-directional DisplayPorts/Thunderbolt ports. The iMac and HP Z1 have one, which lets them be used as a Display for another computer, while that computer is still running. Apple

Re: [Intel-gfx] [PATCH 2/2] [v2] drm/i915: Disable GGTT PTEs on GEN6+ suspend

2013-10-17 Thread Chris Wilson
On Thu, Oct 17, 2013 at 09:41:09AM +0200, Takashi Iwai wrote: At Wed, 16 Oct 2013 18:27:33 +0100, Chris Wilson wrote: On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote: On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote: So clearing the valid bit should result in

[Intel-gfx] [PATCH] drm/i915: Use frame counter for intel_wait_for_vblank() on CTG

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Use the same wait_for_vblank code for CTG that we use for ILK+. Also fix the name of the frame counter register while at it. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/intel_display.c | 8 1

Re: [Intel-gfx] [PATCH 2/2] [v2] drm/i915: Disable GGTT PTEs on GEN6+ suspend

2013-10-17 Thread Takashi Iwai
At Thu, 17 Oct 2013 10:24:07 +0100, Chris Wilson wrote: On Thu, Oct 17, 2013 at 09:41:09AM +0200, Takashi Iwai wrote: At Wed, 16 Oct 2013 18:27:33 +0100, Chris Wilson wrote: On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote: On Wed, Oct 16, 2013 at 05:58:31PM +0100,

Re: [Intel-gfx] [PATCH 07/16] drm/i915: crc support for hsw

2013-10-17 Thread Damien Lespiau
On Wed, Oct 16, 2013 at 10:55:52PM +0200, Daniel Vetter wrote: hw designers decided to change the CRC registers and coalesce them all into one. Otherwise nothing changed. I've opted for a new hsw_ version to grab the crc sample since hsw+1 will have the same crc registers, but different

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Expose latest 200 CRC value for pipe through debugfs

2013-10-17 Thread He, Shuang
Thank you Danmien for helping with this. It's moving so fast. I'm looking forward we could create some automation test for media also Thanks --Shuang -Original Message- From: Lespiau, Damien Sent: Wednesday, October 16, 2013 1:55 AM To: intel-gfx@lists.freedesktop.org Cc:

Re: [Intel-gfx] [IGT PATCH 1/2] intel_opregion_decode: new tool for decoding graphics opregion

2013-10-17 Thread Rodrigo Vivi
On Tue, Oct 8, 2013 at 3:18 PM, Jani Nikula jani.nik...@intel.com wrote: Signed-off-by: Jani Nikula jani.nik...@intel.com --- tools/Makefile.am |1 + tools/intel_opregion_decode.c | 438 + 2 files changed, 439 insertions(+) create

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration

2013-10-17 Thread Rodrigo Vivi
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula jani.nik...@intel.com wrote: The HDMI audio expects HDMI pixel clock to be set in the audio configuration. We've currently just set 0, using 25.2 / 1.001 kHz frequency, which fails with some modes.

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs

2013-10-17 Thread Rodrigo Vivi
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula jani.nik...@intel.com wrote: This will be needed for setting the HDMI pixel clock for audio config. No functional changes. v2: Now with a commit message. Signed-off-by: Jani Nikula

[Intel-gfx] [PATCH] drm/i915: Do hw quiescing first during unload

2013-10-17 Thread Chris Wilson
If we force the hw to idle as our first step during unload, we can abort the unload upon failure. Later we can probe whether the hardware remain active even after we try to shut it down. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_dma.c | 10 ++ 1

[Intel-gfx] [PATCH] drm/i915: don't Oops in debugfs for I915_FBDEV=n

2013-10-17 Thread Daniel Vetter
Failed to properly test this. Reported-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration

2013-10-17 Thread Daniel Vetter
On Thu, Oct 17, 2013 at 09:01:52AM -0300, Rodrigo Vivi wrote: Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula jani.nik...@intel.com wrote: The HDMI audio expects HDMI pixel clock to be set in the audio configuration. We've currently just set 0,

Re: [Intel-gfx] [PATCH] drm/i915: don't Oops in debugfs for I915_FBDEV=n

2013-10-17 Thread Chris Wilson
On Thu, Oct 17, 2013 at 02:37:07PM +0200, Daniel Vetter wrote: Failed to properly test this. Reported-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Chris Wilson ch...@chris-wilson.co.uk Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch Tested-by: Chris Wilson ch...@chris-wilson.co.uk

Re: [Intel-gfx] [PATCH 4/5] drm/i915: take power well refs when needed

2013-10-17 Thread Imre Deak
On Wed, 2013-10-16 at 08:08 -0700, Jesse Barnes wrote: On Wed, 16 Oct 2013 14:10:13 +0300 Imre Deak imre.d...@intel.com wrote: On Tue, 2013-10-15 at 13:40 -0700, Jesse Barnes wrote: On Tue, 15 Oct 2013 16:54:00 -0300 Paulo Zanoni przan...@gmail.com wrote: [...] No that's taken

Re: [Intel-gfx] [PATCH 07/16] drm/i915: crc support for hsw

2013-10-17 Thread Daniel Vetter
On Thu, Oct 17, 2013 at 11:53:49AM +0100, Damien Lespiau wrote: On Wed, Oct 16, 2013 at 10:55:52PM +0200, Daniel Vetter wrote: hw designers decided to change the CRC registers and coalesce them all into one. Otherwise nothing changed. I've opted for a new hsw_ version to grab the crc sample

Re: [Intel-gfx] [PATCH] drm/i915: preserve dispaly init order on ByT

2013-10-17 Thread Artem Bityutskiy
On Wed, 2013-10-16 at 19:46 +0200, Daniel Vetter wrote: On Wed, Oct 16, 2013 at 06:10:41PM +0300, Artem Bityutskiy wrote: From: Artem Bityutskiy artem.bityuts...@linux.intel.com This patch changes HDMI port registration order for the BayTrail platform. The story is that in kernel

[Intel-gfx] [PATCH] drm/i915: Use a spin lock to protect the pipe crc struct

2013-10-17 Thread Damien Lespiau
Daniel pointed out that it was hard to get anything lockless to work correctly, so don't even try for this non critical piece of code and just use a spin lock. Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch Signed-off-by: Damien Lespiau damien.lesp...@intel.com ---

Re: [Intel-gfx] [PATCH] drm/i915: set active format aspect ratio same as picture aspect ratio

2013-10-17 Thread Damien Lespiau
On Wed, May 22, 2013 at 04:48:15PM +0800, Xiong Zhang wrote: HDMI Compliance Testing fail on i915 driver, the error log show: M1-M0=0b00(NO Data) of AVI InfoFrame Packet should correspond to the aspect ratio of the viewed image.Skip because AVI R3-R0 is no 1000 (Same as picture aspect ratio)

[Intel-gfx] [RFC] [PATCH] drm/i915: Require HW contexts (when possible)

2013-10-17 Thread Ben Widawsky
From: Ben Widawsky benjamin.widaw...@intel.com Only compile tested CC: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.c | 5 +--- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/i915_gem.c

Re: [Intel-gfx] [RFC] [PATCH] drm/i915: Require HW contexts (when possible)

2013-10-17 Thread Kenneth Graunke
On 10/17/2013 09:59 AM, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@intel.com Only compile tested CC: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net The code looks good to me (but I didn't test it either). I'm in favor of this happening.

Re: [Intel-gfx] [RFC] [PATCH] drm/i915: Require HW contexts (when possible)

2013-10-17 Thread Ville Syrjälä
On Thu, Oct 17, 2013 at 09:59:43AM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@intel.com Only compile tested CC: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.c | 5 +---

Re: [Intel-gfx] [RFC] [PATCH] drm/i915: Require HW contexts (when possible)

2013-10-17 Thread Ben Widawsky
On Thu, Oct 17, 2013 at 08:52:17PM +0300, Ville Syrjälä wrote: On Thu, Oct 17, 2013 at 09:59:43AM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@intel.com Only compile tested CC: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net

Re: [Intel-gfx] [PATCH] drm/i915: Do hw quiescing first during unload

2013-10-17 Thread Ben Widawsky
On Thu, Oct 17, 2013 at 01:02:53PM +0100, Chris Wilson wrote: If we force the hw to idle as our first step during unload, we can abort the unload upon failure. Later we can probe whether the hardware remain active even after we try to shut it down. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Do hw quiescing first during unload

2013-10-17 Thread Chris Wilson
On Thu, Oct 17, 2013 at 12:07:26PM -0700, Ben Widawsky wrote: On Thu, Oct 17, 2013 at 01:02:53PM +0100, Chris Wilson wrote: If we force the hw to idle as our first step during unload, we can abort the unload upon failure. Later we can probe whether the hardware remain active even after we

[Intel-gfx] [PATCH 0/7] drm/i915: Atomic sprites

2013-10-17 Thread ville . syrjala
Today I heard some grumblings about atomic updates again, so I decided to move the thing forward a bit. This series only makes sprite updates + the accompanying primary enable/disable happen atomically. But it's a decent baby step towards full atomic updates. At least we would get the vblank evade

[Intel-gfx] [PATCH 1/7] drm/i915: Don't disable primary when color keying is used

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com When color keying is used, the primary may not be invisible even though the sprite fully covers it. So check for color keying before deciding to disable the primary plane. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Intel-gfx] [PATCH 2/7] drm/i915: Fix non-scaled sprites for ILK

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com For some reason we're enabling sprite scaling on ILK always. That doesn't work well with the new watermark code that expects to use LP1 watermarks with unscaled sprites. Only enable sprite scaling on ILK when actually needed, just like we do on

[Intel-gfx] [PATCH 3/7] drm/i915: Add i915_get_crtc_scanline()

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Refactor the i915_get_crtc_scanoutpos() code a bit to make the negative values during vblank adjustment optional. For most uses the raw scanline number without such adjustments is easier to use. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 5/7] drm/i915: Make sprite updates atomic

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add a mechanism by which we can evade the leading edge of vblank. This guarantees that no two sprite register writes will straddle on either side of the vblank start, and that means all the writes will be latched together in one atomic operation.

[Intel-gfx] [PATCH 7/7] drm/i915: Add pipe update trace points

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Add trace points for observing the atomic pipe update mechanism. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- drivers/gpu/drm/i915/i915_trace.h | 77 + drivers/gpu/drm/i915/intel_sprite.c |

[Intel-gfx] [PATCH 4/7] drm/i915: Shuffle sprite register writes into a tighter group

2013-10-17 Thread ville . syrjala
From: Ville Syrjälä ville.syrj...@linux.intel.com Group the sprite register writes a bit tighter. We want to write the registers atomically, and so doing the base address/offset artihmetic within the critical section is pointless when it can all be done beforehand. Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Fix non-scaled sprites for ILK

2013-10-17 Thread Chris Wilson
On Thu, Oct 17, 2013 at 10:53:14PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com For some reason we're enabling sprite scaling on ILK always. That doesn't work well with the new watermark code that expects to use LP1 watermarks with unscaled

Re: [Intel-gfx] [PATCH] drm/i915: Do hw quiescing first during unload

2013-10-17 Thread Ben Widawsky
On Thu, Oct 17, 2013 at 08:37:44PM +0100, Chris Wilson wrote: On Thu, Oct 17, 2013 at 12:07:26PM -0700, Ben Widawsky wrote: On Thu, Oct 17, 2013 at 01:02:53PM +0100, Chris Wilson wrote: If we force the hw to idle as our first step during unload, we can abort the unload upon failure. Later

Re: [Intel-gfx] [PATCH] drm/i915: Do hw quiescing first during unload

2013-10-17 Thread Chris Wilson
On Thu, Oct 17, 2013 at 02:04:34PM -0700, Ben Widawsky wrote: On Thu, Oct 17, 2013 at 08:37:44PM +0100, Chris Wilson wrote: On Thu, Oct 17, 2013 at 12:07:26PM -0700, Ben Widawsky wrote: On Thu, Oct 17, 2013 at 01:02:53PM +0100, Chris Wilson wrote: If we force the hw to idle as our first

[Intel-gfx] [PATCH] [v2] drm/i915: Require HW contexts (when possible)

2013-10-17 Thread Ben Widawsky
v2: Fixed the botched locking on init_hw failure in i915_reset (Ville) Call cleanup_ringbuffer on failed context create in init_hw (Ville) Reviewed-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_drv.c | 3 ---

Re: [Intel-gfx] [PATCH 2/2] [v2] drm/i915: Disable GGTT PTEs on GEN6+ suspend

2013-10-17 Thread Todd Previte
On 10/16/13 9:21 AM, Ben Widawsky wrote: Once the machine gets to a certain point in the suspend process, we expect the GPU to be idle. If it is not, we might corrupt memory. Empirically (with an early version of this patch) we have seen this is not the case. We cannot currently explain why the