[Intel-gfx] ✓ Fi.CI.BAT: success for Enhancement to intel_dp_aux_backlight driver (rev6)

== Series Details == Series: Enhancement to intel_dp_aux_backlight driver (rev6) URL : https://patchwork.freedesktop.org/series/21086/ State : success == Summary == Series 21086v6 Enhancement to intel_dp_aux_backlight driver

Re: [Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

Hi Weinan, [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v4.11 next-20170511] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Weinan-Li/drm-i915-gvt-return

Re: [Intel-gfx] [PATCH 07/11] drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation

On Mon, May 08, 2017 at 05:18:58PM +0530, Mahesh Kumar wrote: > DDB minimum requirement may exceed the allocated DDB for CRTC/Pipe. This > patch make changes to fail the flip if minimum requirement for pipe > exceeds the total ddb allocated to the pipe. > Previously it succeeded but making

Re: [Intel-gfx] [PATCH 08/11] drm/i915/skl+: Watermark calculation cleanup

On Mon, May 08, 2017 at 05:18:59PM +0530, Mahesh Kumar wrote: > This patch cleanup/reorganises the watermark calculation functions. > This patch also make use of already available macro > "drm_atomic_crtc_state_for_each_plane_state" to walk through > plane_state list instead of calculating

Re: [Intel-gfx] [PATCH 04/11] drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point

On Mon, May 08, 2017 at 05:18:55PM +0530, Mahesh Kumar wrote: > This patch make changes to calculate adjusted plane pixel rate & > plane downscale amount using fixed_point functions available. > This patch will give uniformity in code, & will help to avoid mixing of > 32bit uint32_t variable for

Re: [Intel-gfx] [PATCH 05/11] drm/i915/skl: Fail the flip if no FB for WM calculation

On Mon, May 08, 2017 at 05:31:30PM +0530, Mahesh Kumar wrote: > Hi, > > > On Monday 08 May 2017 05:18 PM, Lankhorst, Maarten wrote: > > Mahesh Kumar schreef op ma 08-05-2017 om 17:18 [+0530]: > > > Fail the flip if no FB is present but plane_state is set as visible. > > > Above is not a valid

Re: [Intel-gfx] [PATCH 06/11] drm/i915/skl+: no need to memset again

On Mon, May 08, 2017 at 05:18:57PM +0530, Mahesh Kumar wrote: > We are already doing memset of ddb structure at the begining of > skl_allocate_pipe_ddb > function, No need to again do a memset. > > Signed-off-by: Mahesh Kumar Reviewed-by: Matt Roper

Re: [Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

Thanks. Best Regards. Weinan, LI > -Original Message- > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] > Sent: Thursday, May 11, 2017 8:56 PM > To: Li, Weinan Z ; intel-gfx@lists.freedesktop.org; > intel- > gvt-...@lists.freedesktop.org > Cc:

Re: [Intel-gfx] [PATCH v7 3/9] drm/i915: Drop AUX backlight enable check for backlight control

On Thu, 2017-05-11 at 16:02 -0700, Puthikorn Voravootivat wrote: > There are some panel that > (1) does not support display backlight enable via AUX > (2) support display backlight adjustment via AUX > (3) support display backlight enable via eDP BL_ENABLE pin > > The current driver required that

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

On Fri, 12 May 2017 02:12:10 + "Chen, Xiaoguang" wrote: > Hi Alex and Gerd, > > >-Original Message- > >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On > >Behalf Of Alex Williamson > >Sent: Thursday, May 11, 2017 11:45 PM > >To:

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

>-Original Message- >From: Alex Williamson [mailto:alex.william...@redhat.com] >Sent: Friday, May 12, 2017 10:58 AM >To: Chen, Xiaoguang >Cc: Gerd Hoffmann ; Tian, Kevin ; >intel-gfx@lists.freedesktop.org;

[Intel-gfx] [PATCH v7 6/9] drm/i915: Add option to support dynamic backlight via DPCD

This patch adds option to enable dynamic backlight for eDP panel that supports this feature via DPCD register and set minimum / maximum brightness to 0% and 100% of the normal brightness. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/i915_params.c

[Intel-gfx] [PATCH v7 7/9] drm/i915: Restore brightness level in aux backlight driver

Some panel will default to zero brightness when turning the panel off and on again. This patch restores last brightness level back when panel is turning back on. Signed-off-by: Puthikorn Voravootivat Reviewed-by: Dhinakaran Pandiyan ---

Re: [Intel-gfx] [PATCH v7 6/9] drm/i915: Add option to support dynamic backlight via DPCD

On Thu, 2017-05-11 at 16:02 -0700, Puthikorn Voravootivat wrote: > This patch adds option to enable dynamic backlight for eDP > panel that supports this feature via DPCD register and > set minimum / maximum brightness to 0% and 100% of the > normal brightness. > > Signed-off-by: Puthikorn

Re: [Intel-gfx] GPU hang with kernel 4.10rc3

On 11/05/17 23:08, Pavel Machek wrote: > On Mon 2017-01-23 10:39:27, Juergen Gross wrote: >> On 13/01/17 15:41, Juergen Gross wrote: >>> On 12/01/17 10:21, Chris Wilson wrote: On Thu, Jan 12, 2017 at 07:03:25AM +0100, Juergen Gross wrote: > On 11/01/17 18:08, Chris Wilson wrote: >> On

[Intel-gfx] [PATCH v7 3/9] drm/i915: Drop AUX backlight enable check for backlight control

There are some panel that (1) does not support display backlight enable via AUX (2) support display backlight adjustment via AUX (3) support display backlight enable via eDP BL_ENABLE pin The current driver required that (1) must be support to enable (2). This patch drops that requirement.

[Intel-gfx] [PATCH v7 8/9] drm: Add definition for eDP backlight frequency

This patch adds the following definition - Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap register which only use bit 0:4 - Base frequency (27 MHz) for backlight PWM frequency generator. Signed-off-by: Puthikorn Voravootivat Reviewed-by: Dhinakaran Pandiyan

[Intel-gfx] [PATCH v7 5/9] drm/i915: Set backlight mode before enable backlight

We should set backlight mode register before set register to enable the backlight. Signed-off-by: Puthikorn Voravootivat Reviewed-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 4 ++-- 1 file changed, 2

[Intel-gfx] [PATCH v7 4/9] drm/i915: Allow choosing how to adjust brightness if both supported

Add option to allow choosing how to adjust brightness if panel supports both PWM pin and AUX channel. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/i915_params.c| 8 +--- drivers/gpu/drm/i915/i915_params.h| 2 +-

[Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt

Read desired PWM frequency from panel vbt and calculate the value for divider in DPCD address 0x724 and 0x728 to have as many bits as possible for PWM duty cyle for granularity of brightness adjustment while the frequency is still within 25% of the desired frequency. Signed-off-by: Puthikorn

[Intel-gfx] [PATCH v7 0/9] Enhancement to intel_dp_aux_backlight driver

This patch set contain 9 patches. - First five patches fix bug in the driver and allow choosing which way to adjust brightness if both PWM pin and AUX are supported - Next patch adds enable DBC by default - Next patch makes the driver restore last brightness level after turning display off and

[Intel-gfx] [PATCH v7 1/9] drm/i915: Fix cap check for intel_dp_aux_backlight driver

intel_dp_aux_backlight driver should check for the DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP before enable the driver. Signed-off-by: Puthikorn Voravootivat Reviewed-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1

[Intel-gfx] [PATCH v7 2/9] drm/i915: Correctly enable backlight brightness adjustment via DPCD

intel_dp_aux_enable_backlight() assumed that the register BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01 (DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize. This patch fixed that by handling all cases of that register. Signed-off-by: Puthikorn Voravootivat

Re: [Intel-gfx] [PATCH 02/11] drm/i915: Add more wrapper for fixed_point_16_16 operations

On Mon, May 08, 2017 at 05:18:53PM +0530, Mahesh Kumar wrote: > This patch adds few wrapper to perform fixed_point_16_16 operations > mul_u32_fixed_16_16_round_up : Multiplies u32 and fixed_16_16_t > variables & returns u32 result with >

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Use fixed_16_16 wrapper for division operation

On Mon, May 08, 2017 at 05:18:54PM +0530, Mahesh Kumar wrote: > Don't use fixed_16_16 structure members directly, instead use wrapper to > perform fixed_16_16 division operation. > > Signed-off-by: Mahesh Kumar Reviewed-by: Matt Roper > ---

Re: [Intel-gfx] [PATCH 00/11] Implement DDB algorithm and WM cleanup

On Mon, May 08, 2017 at 05:18:51PM +0530, Mahesh Kumar wrote: > This series implements new DDB allocation algorithm to solve the cases, > where we have sufficient DDB available to enable multiple planes, But > due to the current algorithm not dividing it properly among planes, we > end-up failing

Re: [Intel-gfx] [PATCH 01/11] drm/i915: fix naming of fixed_16_16 wrapper.

On Mon, May 08, 2017 at 05:18:52PM +0530, Mahesh Kumar wrote: > fixed_16_16_div_round_up(_u64), wrapper for fixed_16_16 division > operation don't really round_up the result. Wrapper round_up only the > fraction part of the result to make it 16-bit. > This patch eliminates round_up keyword from

Re: [Intel-gfx] [PATCH v2 5/5] ACPI: button: Obselete acpi_lid_open() invocations

Hi, > From: Benjamin Tissoires [mailto:benjamin.tissoi...@gmail.com] > Subject: Re: [PATCH v2 5/5] ACPI: button: Obselete acpi_lid_open() invocations > > On Tue, May 9, 2017 at 9:02 AM, Lv Zheng wrote: > > Since notification side has been changed to always notify kernel

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

Hi Alex and Gerd, >-Original Message- >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On >Behalf Of Alex Williamson >Sent: Thursday, May 11, 2017 11:45 PM >To: Gerd Hoffmann >Cc: Tian, Kevin ;

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Detect USB-C specific dongles before reducing M and N

== Series Details == Series: drm/i915: Detect USB-C specific dongles before reducing M and N URL : https://patchwork.freedesktop.org/series/24254/ State : failure == Summary == Series 24254v1 drm/i915: Detect USB-C specific dongles before reducing M and N

[Intel-gfx] [PATCH 1/2] drm/i915: Fix hw state verifier access to crtc->state.

We shouldn't inspect crtc->state, instead grab the crtc state. At this point the hw state verifier should be able to run even if crtc->state has been updated (which cannot currently happen). Signed-off-by: Maarten Lankhorst ---

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove vma unpin in intel_plane_destroy

On Thu, May 11, 2017 at 10:28:44AM +0200, Maarten Lankhorst wrote: > commit a667fb402c1e856209bf9e77ba41fc1cf356b867 > Author: Maarten Lankhorst > Date: Thu Dec 15 15:29:44 2016 +0100 > > drm/i915: Disable all crtcs during driver unload, v2. > > made

Re: [Intel-gfx] [PATCH v1 4/4] drm/i915: enable guest full ppgtt when device model supports

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote: > Add full ppgtt capability check in guest i915 driver and enable the full > ppgtt in guest only when device mode supports. > > Signed-off-by: Tina Zhang > @@ -1909,6 +1909,7 @@ struct i915_workarounds { >   >  struct

[Intel-gfx] [PATCH v2] drm/i915/skl+: consider max supported plane pixel rate while scaling

A display resolution is only supported if it meets all the restrictions below for Maximum Pipe Pixel Rate. The display resolution must fit within the maximum pixel rate output from the pipe. Make sure that the display pipe is able to feed pixels at a rate required to support the desired

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove the duplicated size check in i915_gem_dmabuf_mmap()

== Series Details == Series: drm/i915: remove the duplicated size check in i915_gem_dmabuf_mmap() URL : https://patchwork.freedesktop.org/series/24272/ State : success == Summary == Series 24272v1 drm/i915: remove the duplicated size check in i915_gem_dmabuf_mmap()

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

Hi Alex, >-Original Message- >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On >Behalf Of Alex Williamson >Sent: Friday, May 05, 2017 11:11 PM >To: Gerd Hoffmann >Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; linux-

Re: [Intel-gfx] [PATCH 11/11] drm/i915/skl+: consider max supported plane pixel rate while scaling

Hi, Thanks for review. On Wednesday 10 May 2017 06:52 PM, Maarten Lankhorst wrote: Op 08-05-17 om 13:49 schreef Mahesh Kumar: A display resolution is only supported if it meets all the restrictions below for Maximum Pipe Pixel Rate. The display resolution must fit within the maximum pixel

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: remove the duplicated size check in i915_gem_dmabuf_mmap()

Hi, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Patchwork > Sent: Thursday, May 11, 2017 9:23 AM > To: hw...@emeril.freedesktop.org; Hwang, Dongseong > > Cc: intel-gfx@lists.freedesktop.org > Subject:

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Detect USB-C specific dongles before reducing M and N

Hi, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Patchwork > Sent: Thursday, May 11, 2017 9:06 AM > To: Taylor, Clinton A > Cc: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] ✗ Fi.CI.BAT:

Re: [Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

> -Original Message- > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] > Sent: Wednesday, May 10, 2017 6:43 PM > To: Li, Weinan Z ; intel-gfx@lists.freedesktop.org; > intel- > gvt-...@lists.freedesktop.org > Cc: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: remove the duplicated size check in i915_gem_dmabuf_mmap()

On Wed, May 10, 2017 at 09:05:37PM -0700, Dongseong Hwang wrote: > dma_buf_mmap_internal() already checks for overflowing the buffer's size. > In addition, the check in i915_gem_dmabuf_mmap() is incomplete, which doesn't > consider a page offset. Please read

Re: [Intel-gfx] [PATCH v1 2/4] drm/i915: introduce vgt_caps to pvinfo

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote: > vgt_caps is used for guest i915 driver to get the vgpu capabilities > from the device model. > > Signed-off-by: Tina Zhang > +++ b/drivers/gpu/drm/i915/i915_pvinfo.h > @@ -58,7 +58,8 @@ struct vgt_if { >  

[Intel-gfx] [PATCH 2/2] drm/i915: Remove vma unpin in intel_plane_destroy

commit a667fb402c1e856209bf9e77ba41fc1cf356b867 Author: Maarten Lankhorst Date: Thu Dec 15 15:29:44 2016 +0100 drm/i915: Disable all crtcs during driver unload, v2. made sure that all crtc's are disabled on driver unload, but only the following commit

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix hw state verifier access to crtc->state.

== Series Details == Series: series starting with [1/2] drm/i915: Fix hw state verifier access to crtc->state. URL : https://patchwork.freedesktop.org/series/24281/ State : success == Summary == Series 24281v1 Series without cover letter

Re: [Intel-gfx] [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro

On Thu, Apr 06, 2017 at 12:15:07PM -0700, Rodrigo Vivi wrote: > From: Paulo Zanoni > > We're going to use it in the next commits. > > Signed-off-by: Paulo Zanoni > Signed-off-by: Rodrigo Vivi Reviewed-by: Jim Bride

[Intel-gfx] [PATCH 13/22] drm/i915: expose _SUBSLICE_MASK GETPARM

From: Robert Bragg Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub

[Intel-gfx] [PATCH 16/22] drm/i915/perf: Add OA unit support for Gen 8+

From: Robert Bragg Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all share (more-or-less) the same OA unit design. Of particular note in comparison to Haswell: some OA unit HW config state has become per-context state and as a consequence it is somewhat

[Intel-gfx] [PATCH 15/22] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs

From: Robert Bragg Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic render metrics on Broadwell, Cherryview, Skylake and Broxton. These are auto generated from an XML description of metric sets, currently maintained in gputop, ref:

[Intel-gfx] [PATCH 22/22] drm/i915/perf: add GLK support

Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/Makefile |3 +- drivers/gpu/drm/i915/i915_oa_glk.c | 2600 drivers/gpu/drm/i915/i915_oa_glk.h | 38 + drivers/gpu/drm/i915/i915_perf.c | 15 +- 4 files

[Intel-gfx] [PATCH 14/22] drm/i915/perf: rework mux configurations queries

Gen8+ might have mux configurations per slices/subslices. Depending on whether slices/subslices have been fused off, only part of the configuration needs to be applied. This change reworks the mux configurations query mechanism to allow more than one set of registers to be programmed.

[Intel-gfx] [PATCH 12/22] drm/i915: expose _SLICE_MASK GETPARM

From: Robert Bragg Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice

[Intel-gfx] [PATCH 18/22] drm/i915/perf: per-gen timebase for checking sample freq

From: Robert Bragg An oa_exponent_to_ns() utility and per-gen timebase constants where recently removed when updating the tail pointer race condition WA, and this restores those so we can update the _PROP_OA_EXPONENT validation done in read_properties_unlocked() to not

[Intel-gfx] [PATCH 19/22] drm/i915/perf: remove perf.hook_lock

From: Robert Bragg In earlier iterations of the i915-perf driver we had a number of callbacks/hooks from other parts of the i915 driver to e.g. notify us when a legacy context was pinned and these could run asynchronously with respect to the stream file operations and might

[Intel-gfx] [PATCH 20/22] drm/i915: add KBL GT2/GT3 check macros

Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e9df52031eae..88906c79f982 100644 ---

[Intel-gfx] [PATCH 03/22] drm/i915/perf: avoid read back of head register

From: Robert Bragg There's no need for the driver to keep reading back the head pointer from hardware since the hardware doesn't update it automatically. This way we can treat any invalid head pointer value as a software/driver bug instead of spurious hardware behaviour.

[Intel-gfx] [PATCH 08/22] drm/i915/perf: rate limit spurious oa report notice

From: Robert Bragg This change is pre-emptively aiming to avoid a potential cause of kernel logging noise in case some condition were to result in us seeing invalid OA reports. The workaround for the OA unit's tail pointer race condition is what avoids the primary known

[Intel-gfx] [PATCH 06/22] drm/i915/perf: improve invalid OA format debug message

From: Robert Bragg A minor improvement to debugging output Signed-off-by: Robert Bragg Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_perf.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH 05/22] drm/i915/perf: improve tail race workaround

From: Robert Bragg There's a HW race condition between OA unit tail pointer register updates and writes to memory whereby the tail pointer can sometimes get ahead of what's been written out to the OA buffer so far (in terms of what's visible to the CPU). Although this can

[Intel-gfx] [PATCH 04/22] drm/i915/perf: no head/tail ref in gen7_oa_read

From: Robert Bragg This avoids redundantly passing an (inout) head and tail pointer to gen7_append_oa_reports() from gen7_oa_read which doesn't need to reference either itself. Moving the head/tail reads and writes into gen7_append_oa_reports should have no functional

[Intel-gfx] [PATCH 11/22] drm/i915: Record the sseu configuration per-context

From: Chris Wilson In the next patch, we will expose the ability to reconfigure the slices, subslice and eu per context. To facilitate that, store the current configuration on the context, which is initially set to the device default upon creation. Signed-off-by: Chris

[Intel-gfx] [PATCH 02/22] drm/i915/perf: avoid poll, read, EAGAIN busy loops

From: Robert Bragg If the function for checking whether there is OA buffer data available (during a poll or blocking read) has false positives then we want to avoid a situation where the subsequent read() returns EAGAIN (after a more accurate check) followed by a poll()

[Intel-gfx] [PATCH 09/22] drm/i915: Record both min/max eu_per_subslice in sseu_dev_info

From: Chris Wilson When we query the available eu on each subslice, we currently only report the max. It would also be useful to report the minimum found as well. When we set RPCS (power gating over the EU), we can also specify both the min and max number of eu to

[Intel-gfx] [PATCH 10/22] drm/i915: Program RPCS for Broadwell

From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the

[Intel-gfx] [PATCH 01/22] drm/i915/perf: fix gen7_append_oa_reports comment

From: Robert Bragg If I'm going to complain about a back-to-front convention then the least I can do is not muddle the comment up too. Signed-off-by: Robert Bragg Reviewed-by: Matthew Auld ---

[Intel-gfx] [PATCH v12 00/22] Enable OA unit for Gen 8 and 9 in i915 perf

Hi all, Here are the changes from the previous series : * Included patches 9, 10 & 11 from Chris to have sseu configuration stored per context (but not exposed to userspace) * In patches 12 & 13 querying the slice/subslice configuration now returns the configuration locked in by the OA

[Intel-gfx] [PATCH 07/22] drm/i915/perf: better pipeline aged/aging tail updates

From: Robert Bragg This updates the tail pointer race workaround handling to updating the 'aged' pointer before looking to start aging a new one. There's the possibility that there is already new data available and so we can immediately start aging a new pointer without

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

On Thu, 11 May 2017 15:27:53 +0200 Gerd Hoffmann wrote: > Hi, > > > While read the framebuffer region we have to tell the vendor driver which > > framebuffer we want to read? There are two framebuffers now in KVMGT that > > is primary and cursor. > > There are two methods

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Dump the GuC stage descriptor pool in debugfs (rev2)

On ke, 2017-05-10 at 22:24 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/guc: Dump the GuC stage descriptor pool in debugfs (rev2) > URL   : https://patchwork.freedesktop.org/series/24051/ > State : success Fixed the checkpatch.pl complaints and merged the patch, thanks for

Re: [Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > The Analogix 7737 DP to HDMI converter requires reduced N and M values when > to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9. I'm not happy, but I also see no

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: set initialised only when init_context callback is NULL

== Series Details == Series: drm/i915: set initialised only when init_context callback is NULL URL : https://patchwork.freedesktop.org/series/24286/ State : success == Summary == Series 24286v1 drm/i915: set initialised only when init_context callback is NULL

Re: [Intel-gfx] [PATCH v4] drm/i915/gvt: return the correct usable aperture size under gvt environment

On to, 2017-05-11 at 06:51 +, Li, Weinan Z wrote: > > > > -Original Message- > > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] > > Sent: Wednesday, May 10, 2017 6:43 PM > > To: Li, Weinan Z ; intel-gfx@lists.freedesktop.org; > > intel- > >

[Intel-gfx] [PATCH v4 11/11] drm/i915/skl+: consider max supported plane pixel rate while scaling

A display resolution is only supported if it meets all the restrictions below for Maximum Pipe Pixel Rate. The display resolution must fit within the maximum pixel rate output from the pipe. Make sure that the display pipe is able to feed pixels at a rate required to support the desired

Re: [Intel-gfx] [PATCH] drm/i915: Consistent ordering of tracepoint binary data

On 11/05/2017 14:07, Chris Wilson wrote: On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin For userspace receiving binary data it is easier if all related request tracepoints emit the binary data in the same order of dev, ring,

Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: disable GVT-g if host GuC submission is enabled

> -Original Message- > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] > Sent: Thursday, May 11, 2017 8:50 PM > To: Dong, Chuanxiao ; intel-gvt- > d...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2]

[Intel-gfx] ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev6)

== Series Details == Series: Implement DDB algorithm and WM cleanup (rev6) URL : https://patchwork.freedesktop.org/series/20376/ State : success == Summary == Series 20376v6 Implement DDB algorithm and WM cleanup https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/6/mbox/ Test

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Consistent ordering of tracepoint binary data

== Series Details == Series: drm/i915: Consistent ordering of tracepoint binary data URL : https://patchwork.freedesktop.org/series/24293/ State : success == Summary == Series 24293v1 drm/i915: Consistent ordering of tracepoint binary data

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

Hi, > While read the framebuffer region we have to tell the vendor driver which > framebuffer we want to read? There are two framebuffers now in KVMGT that is > primary and cursor. > There are two methods to implement this: > 1) write the plane id first and then read the framebuffer. > 2)

Re: [Intel-gfx] [PATCH] drm/i915: Consistent ordering of tracepoint binary data

On Thu, May 11, 2017 at 02:07:35PM +0100, Chris Wilson wrote: > On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > > > For userspace receiving binary data it is easier if all related > > request tracepoints emit the binary data

[Intel-gfx] [PATCH] drm/i915: Consistent ordering of tracepoint binary data

From: Tvrtko Ursulin For userspace receiving binary data it is easier if all related request tracepoints emit the binary data in the same order of dev, ring, ctx, seqno, ... Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson

Re: [Intel-gfx] [RFC] drm/i915: Allow the UMD to configure their own power clock state

On ke, 2017-05-10 at 08:33 +, Oscar Mateo wrote: > > > On 05/10/2017 01:28 PM, Daniel Vetter wrote: > > > > On Wed, May 10, 2017 at 2:59 PM, Joonas Lahtinen > > wrote: > > > > > > > > > > > @@ -841,6 +847,11 @@ static int gen9_init_workarounds(struct > >

Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: disable GVT-g if host GuC submission is enabled

On to, 2017-05-11 at 02:33 +, Dong, Chuanxiao wrote: > > > > > -Original Message- > > From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com] > > Sent: Wednesday, May 10, 2017 8:48 PM > > To: Dong, Chuanxiao ; intel-gvt- > >

Re: [Intel-gfx] [PATCH] drm/i915: Consistent ordering of tracepoint binary data

On Thu, May 11, 2017 at 02:00:45PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > For userspace receiving binary data it is easier if all related > request tracepoints emit the binary data in the same order of > dev, ring, ctx, seqno, ... We decided that dev,

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 02:57 AM, Jani Nikula wrote: From: Clint Taylor The Analogix 7737 DP to HDMI converter requires reduced M and N values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9 via the DPCD quirk list. v2 by Jani: Rebased on the

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf (rev11)

== Series Details == Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev11) URL : https://patchwork.freedesktop.org/series/20084/ State : success == Summary == Series 20084v11 Enable OA unit for Gen 8 and 9 in i915 perf

Re: [Intel-gfx] [PATCH 1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

On 05/11/2017 02:57 AM, Jani Nikula wrote: Face the fact, there are Display Port sink and branch devices out there in the wild that don't follow the Display Port specifications, or they have bugs, or just otherwise require special treatment. Start a common quirk database the drivers can query

Re: [Intel-gfx] [PATCH] drm/i915: Detect USB-C specific dongles before reducing M and N

On 05/11/2017 03:03 AM, Jani Nikula wrote: On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote: From: Clint Taylor The Analogix 7737 DP to HDMI converter requires reduced N and M values when to operate correctly at HBR2. Detect this IC by its OUI value of

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

== Series Details == Series: series starting with [1/2] drm/dp: start a DPCD based DP sink/branch device quirk database URL : https://patchwork.freedesktop.org/series/24282/ State : warning == Summary == Series 24282v1 Series without cover letter

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix hw state verifier access to crtc->state.

On Thu, May 11, 2017 at 10:28:43AM +0200, Maarten Lankhorst wrote: > We shouldn't inspect crtc->state, instead grab the crtc state. > At this point the hw state verifier should be able to run even if > crtc->state has been updated (which cannot currently happen). > > Signed-off-by: Maarten

[Intel-gfx] ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev5)

== Series Details == Series: Implement DDB algorithm and WM cleanup (rev5) URL : https://patchwork.freedesktop.org/series/20376/ State : success == Summary == Series 20376v5 Implement DDB algorithm and WM cleanup https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/5/mbox/

[Intel-gfx] [PATCH 2/2] drm/i915: Detect USB-C specific dongles before reducing M and N

From: Clint Taylor The Analogix 7737 DP to HDMI converter requires reduced M and N values when to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9 via the DPCD quirk list. v2 by Jani: Rebased on the DP quirk database Fixes: 9a86cda07af2

[Intel-gfx] [PATCH 1/2] drm/dp: start a DPCD based DP sink/branch device quirk database

Face the fact, there are Display Port sink and branch devices out there in the wild that don't follow the Display Port specifications, or they have bugs, or just otherwise require special treatment. Start a common quirk database the drivers can query based on OUI (with the option of expanding to

[Intel-gfx] [PATCH] drm/i915: set initialised only when init_context callback is NULL

initialised is fixup by the GVT shadow context as true to avoid the init from the host because it cannot take the settings from the host. Add a check to let host driver only overwrite it when the init callback is NULL Cc: Chris Wilson Signed-off-by: Chuanxiao Dong

Re: [Intel-gfx] [PATCH 11/11] drm/i915/skl+: consider max supported plane pixel rate while scaling

On Thursday 11 May 2017 03:18 PM, Maarten Lankhorst wrote: Op 11-05-17 om 10:36 schreef Mahesh Kumar: Hi, Thanks for review. On Wednesday 10 May 2017 06:52 PM, Maarten Lankhorst wrote: Op 08-05-17 om 13:49 schreef Mahesh Kumar: A display resolution is only supported if it meets all the

Re: [Intel-gfx] [PATCH 11/11] drm/i915/skl+: consider max supported plane pixel rate while scaling

Op 11-05-17 om 10:36 schreef Mahesh Kumar: > Hi, > > Thanks for review. > > On Wednesday 10 May 2017 06:52 PM, Maarten Lankhorst wrote: >> Op 08-05-17 om 13:49 schreef Mahesh Kumar: >>> A display resolution is only supported if it meets all the restrictions >>> below for Maximum Pipe Pixel Rate.

Re: [Intel-gfx] [PATCH v1 3/4] drm/i915/gvt: provide full ppgtt capability for guest i915 driver

On to, 2017-05-11 at 10:33 +0800, Tina Zhang wrote: > This patch is to provide full ppgtt capability for guest i915 driver. > > Signed-off-by: Tina Zhang > @@ -53,6 +53,10 @@ enum vgt_g2v_type { >   VGT_G2V_MAX, >  }; >   > +enum vgt_caps_type { > +

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix hw state verifier access to crtc->state.

Op 11-05-17 om 11:23 schreef Daniel Vetter: > On Thu, May 11, 2017 at 10:28:43AM +0200, Maarten Lankhorst wrote: >> We shouldn't inspect crtc->state, instead grab the crtc state. >> At this point the hw state verifier should be able to run even if >> crtc->state has been updated (which cannot

Re: [Intel-gfx] [CI v4 1/3] drm/i915/guc: Move notification code into virtual function

On ke, 2017-05-10 at 12:59 +, Michal Wajdeczko wrote: > Prepare for alternate GuC notification mechanism. > > Signed-off-by: Michal Wajdeczko > Cc: Joonas Lahtinen > Cc: Daniele Ceraolo Spurio >

Re: [Intel-gfx] [PATCH v5 6/9] drm/i915: Support dynamic backlight via DPCD register

Fair enough. Will add kernel switch in next version. On Wed, May 10, 2017 at 6:26 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Wed, 2017-05-03 at 17:28 -0700, Puthikorn Voravootivat wrote: > > This patch enables dynamic backlight by default for eDP > > panel that

Re: [Intel-gfx] [PATCH v6 3/9] drm/i915: Drop AUX backlight enable check for backlight control

On Wed, May 10, 2017 at 5:39 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Tue, 2017-05-09 at 16:40 -0700, Puthikorn Voravootivat wrote: > > There are some panel that > > (1) does not support display backlight enable via AUX > > (2) support display backlight adjustment via

Re: [Intel-gfx] GPU hang with kernel 4.10rc3

On Mon 2017-01-23 10:39:27, Juergen Gross wrote: > On 13/01/17 15:41, Juergen Gross wrote: > > On 12/01/17 10:21, Chris Wilson wrote: > >> On Thu, Jan 12, 2017 at 07:03:25AM +0100, Juergen Gross wrote: > >>> On 11/01/17 18:08, Chris Wilson wrote: > On Wed, Jan 11, 2017 at 05:33:34PM +0100,

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