[Intel-gfx] [PATCH igt] igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

Michal wants to limit machines that can do preemption, which means that we no longer can assume that if we have a scheduler for execbuf, that implies we have preemption. Signed-off-by: Chris Wilson --- tests/gem_exec_schedule.c | 35 +++

Re: [Intel-gfx] [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare

Shouldn't we filter them out per platform? Anyways it is good for me Reviewed-by: Rodrigo Vivi On Fri, Sep 22, 2017 at 08:53:42PM +, Paulo Zanoni wrote: > Looks like we were missing them. > > Signed-off-by: Paulo Zanoni > --- >

[Intel-gfx] [PATCH igt 1/3] benchmark/gem_busy: Compare polling with syncobj_wait

Signed-off-by: Chris Wilson --- benchmarks/gem_busy.c | 73 ++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/benchmarks/gem_busy.c b/benchmarks/gem_busy.c index f050454b..9649ea02 100644 ---

[Intel-gfx] [PATCH igt 2/3] benchmarks/gem_syslatency: Apply vmpressure, measure page allocation

Signed-off-by: Chris Wilson --- benchmarks/gem_syslatency.c | 86 +++-- 1 file changed, 83 insertions(+), 3 deletions(-) diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c index 4ed23638..b8788497 100644 ---

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Wrap context schedule notification

== Series Details == Series: series starting with [1/2] drm/i915: Wrap context schedule notification URL : https://patchwork.freedesktop.org/series/30854/ State : success == Summary == Series 30854v1 series starting with [1/2] drm/i915: Wrap context schedule notification

[Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Ignore set-priority failures on old kernels

When plugging the device, we need to submit batches at highest priority so that they cannot be gazumped by the queued requests. On older kernels that do not support the user changing context priority, all contexts therefore have max priority and we can ignore the error. Signed-off-by: Chris

[Intel-gfx] ✓ Fi.CI.IGT: success for huge gtt pages (rev9)

== Series Details == Series: huge gtt pages (rev9) URL : https://patchwork.freedesktop.org/series/25118/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test perf: Subgroup polling:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: Be less aggressive about changing link config on eDP (rev4)

== Series Details == Series: drm/i915/edp: Be less aggressive about changing link config on eDP (rev4) URL : https://patchwork.freedesktop.org/series/28588/ State : success == Summary == Series 28588v4 drm/i915/edp: Be less aggressive about changing link config on eDP

Re: [Intel-gfx] [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare

Em Seg, 2017-09-25 às 16:16 -0700, Rodrigo Vivi escreveu: > Shouldn't we filter them out per platform? Yes, although doing it like this doesn't hurt much. See the cover letter: we can probably organize our structs in per-platform unions or something like that. Thanks for the review. > >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info

I wonder why are we adding all of this to debugfs that can be checked with intel_reg dumps... Assuming it will be already noisy on dmesg if this and HW missmatch... But yeap, since we were missing the checks and it is probably making our life easier, let's move with it and keep everything in

[Intel-gfx] ✓ Fi.CI.IGT: success for IGT PMU support (rev4)

== Series Details == Series: IGT PMU support (rev4) URL : https://patchwork.freedesktop.org/series/28253/ State : success == Summary == Test gem_eio: Subgroup in-flight: pass -> DMESG-WARN (shard-hsw) fdo#102886 +3 Test kms_busy: Subgroup

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915 PMU and engine busy stats (rev12)

== Series Details == Series: i915 PMU and engine busy stats (rev12) URL : https://patchwork.freedesktop.org/series/27488/ State : failure == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test kms_cursor_legacy: Subgroup

[Intel-gfx] [PATCH igt 3/3] benchmarks/gem_exec_fault: Update for tryhard kernels.

Signed-off-by: Chris Wilson Cc: Matthew Auld --- benchmarks/gem_exec_fault.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c index

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() (rev2)

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() (rev2) URL : https://patchwork.freedesktop.org/series/30838/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL

Re: [Intel-gfx] [PATCH igt] igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

Quoting Chris Wilson (2017-09-25 21:48:35) > Michal wants to limit machines that can do preemption, which means that > we no longer can assume that if we have a scheduler for execbuf, that > implies we have preemption. The alternative to a separate param is to use capability bits in

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION URL : https://patchwork.freedesktop.org/series/30860/ State : success == Summary == IGT patchset tested on top of latest successful build c117213c06d0f47937c1f225ebead5e1fe8c7a0e

Re: [Intel-gfx] [PATCH] drm/i915: Mark wait_for_engine() as maybe_unused

On Fri, Aug 25, 2017 at 10:09:45AM -0700, Matthias Kaehlcke wrote: > The only call of wait_for_engine() is wrapped in a GEM_WARN_ON macro, > which confusingly suppresses the call unless CONFIG_DRM_I915_DEBUG_GEM > is set. > > According to http://www.spinics.net/lists/intel-gfx/msg128768.html the

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Wrap context schedule notification

== Series Details == Series: series starting with [1/2] drm/i915: Wrap context schedule notification URL : https://patchwork.freedesktop.org/series/30854/ State : failure == Summary == Test kms_cursor_legacy: Subgroup flip-vs-cursor-crc-legacy: pass -> FAIL

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/gem_exec_schedule: Ignore set-priority failures on old kernels (rev2)

== Series Details == Series: igt/gem_exec_schedule: Ignore set-priority failures on old kernels (rev2) URL : https://patchwork.freedesktop.org/series/30855/ State : success == Summary == Test gem_exec_schedule: Subgroup fifo-render: fail -> PASS

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add module parameter to en-/disable hw color correction.

On Fri, Sep 15, 2017 at 05:48:25PM +0200, Mario Kleiner wrote: > The new module parameter enable_hw_color_correction defaults to > true, to retain the current behaviour. If set to false, it will > disable all hardware color correction, like gamma/degamma and > csc. > > This is useful for

Re: [Intel-gfx] [PATCH] drm/i915: Mark wait_for_engine() as maybe_unused

Signed-off-by: Nick Desaulniers ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION URL : https://patchwork.freedesktop.org/series/30860/ State : success == Summary == Test prime_mmap: Subgroup test_userptr: dmesg-warn -> PASS (shard-hsw) fdo#102939

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/edp: Be less aggressive about changing link config on eDP (rev4)

== Series Details == Series: drm/i915/edp: Be less aggressive about changing link config on eDP (rev4) URL : https://patchwork.freedesktop.org/series/28588/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote: > On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju wrote: > > Add defines for dpcd register 2009 (synchronization latency > > in sink). > > > > Cc: Rodrigo Vivi > > CC: Puthikorn Voravootivat

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] benchmark/gem_busy: Compare polling with syncobj_wait

== Series Details == Series: series starting with [1/3] benchmark/gem_busy: Compare polling with syncobj_wait URL : https://patchwork.freedesktop.org/series/30858/ State : success == Summary == Test prime_mmap: Subgroup test_userptr: dmesg-warn -> PASS

Re: [Intel-gfx] [PATCH] drm/atomic: Make async plane update checks actually work as intended.

On Mon, Sep 25, 2017 at 08:43:44AM +0200, Maarten Lankhorst wrote: > Op 24-09-17 om 16:33 schreef Dmitry Osipenko: > > On 04.09.2017 13:48, Maarten Lankhorst wrote: > >> By always keeping track of the last commit in plane_state, we know > >> whether there is an active update on the plane or not.

Re: [Intel-gfx] [PATCH] drm/i915: Don't rmw PIPESTAT enable bits

On Mon, Sep 25, 2017 at 01:33:18PM +0300, Imre Deak wrote: > On Thu, Sep 14, 2017 at 06:17:31PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > i830 seems to occasionally forget the PIPESTAT enable bits when > > we read the register. These aren't the

[Intel-gfx] [PATCH v2] drm/i915/execlists: Cache the last priolist lookup

From: Michał Winiarski Avoid the repeated rbtree lookup for each request as we unwind them by tracking the last priolist. v2: Fix up my unhelpful suggestion of using default_priolist. Signed-off-by: Michał Winiarski Signed-off-by: Chris

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible

== Series Details == Series: series starting with [v2,1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible URL : https://patchwork.freedesktop.org/series/30833/ State : success == Summary == Test kms_setmode: Subgroup basic: pass -> FAIL

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable scanline read based on frame timestamps

== Series Details == Series: drm/i915: Enable scanline read based on frame timestamps URL : https://patchwork.freedesktop.org/series/30841/ State : success == Summary == Series 30841v1 drm/i915: Enable scanline read based on frame timestamps

[Intel-gfx] [PATCH 3/3] drm/i915/execlists: Cache the last priolist lookup

From: Michał Winiarski Avoid the repeated rbtree lookup for each request as we unwind them by tracking the last priolist. Signed-off-by: Michał Winiarski Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

Just rearrange the code slightly to trim the number of iterations required. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c

Re: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

Chris Wilson writes: > Just rearrange the code slightly to trim the number of iterations > required. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/intel_lrc.c | 17 ++--- > 1 file changed, 10 insertions(+), 7

Re: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

Quoting Mika Kuoppala (2017-09-25 14:00:17) > Chris Wilson writes: > > > Just rearrange the code slightly to trim the number of iterations > > required. > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/intel_lrc.c | 17

Re: [Intel-gfx] [PATCH] drm/i915: Don't rmw PIPESTAT enable bits

Quoting Ville Syrjälä (2017-09-25 15:05:51) > On Fri, Sep 15, 2017 at 01:03:36PM +0300, Ville Syrjälä wrote: > > On Thu, Sep 14, 2017 at 09:37:37PM +0100, Chris Wilson wrote: > > > Quoting Ville Syrjala (2017-09-14 16:17:31) > > > > From: Ville Syrjälä > > > > > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Read timings from the correct transcoder in intel_crtc_mode_get()

Quoting ville.syrj...@linux.intel.com (2016-04-01 16:37:25) > From: Ville Syrjälä > > intel_crtc->config->cpu_transcoder isn't yet filled out when > intel_crtc_mode_get() gets called during output probing, so we should > not use it there. Instead

Re: [Intel-gfx] [PATCH 2/3] drm/i915/execlists: Move request unwinding to a separate function

Quoting Mika Kuoppala (2017-09-25 13:55:26) > Chris Wilson writes: > > > In the future, we will want to unwind requests following a preemption > > point. This requires the same steps as for unwinding upon a reset, so > > extract the existing code to a separate function

[Intel-gfx] [PATCH v8] drm/i915: Enable scanline read based on frame timestamps

From: Uma Shankar For certain platforms on certain encoders, timings are driven from port instead of pipe. Thus, we can't rely on pipe scanline registers to get the timing information. Some cases scanline register read will not be functional. This is causing vblank evasion

Re: [Intel-gfx] [PATCH 3/3] drm/i915/execlists: Cache the last priolist lookup

Quoting Chris Wilson (2017-09-25 13:49:29) > From: Michał Winiarski > > Avoid the repeated rbtree lookup for each request as we unwind them by > tracking the last priolist. > > Signed-off-by: Michał Winiarski > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH 2/3] drm/i915/execlists: Move request unwinding to a separate function

Chris Wilson writes: > In the future, we will want to unwind requests following a preemption > point. This requires the same steps as for unwinding upon a reset, so > extract the existing code to a separate function for later use. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read based on frame timestamps

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Ville Syrjälä >Sent: Monday, September 25, 2017 6:46 PM >To: Srinivas, Vidya >Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Speed up DMC firmware loading (rev4)

Quoting Patchwork (2017-09-05 16:10:55) > == Series Details == > > Series: drm/i915: Speed up DMC firmware loading (rev4) > URL : https://patchwork.freedesktop.org/series/29688/ > State : success > > == Summary == > > shard-hswtotal:2255 pass:1225 dwarn:0 dfail:0 fail:15

Re: [Intel-gfx] [PATCH 2/3] drm/i915/execlists: Move request unwinding to a separate function

Chris Wilson writes: > In the future, we will want to unwind requests following a preemption > point. This requires the same steps as for unwinding upon a reset, so > extract the existing code to a separate function for later use. > > Signed-off-by: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read based on frame timestamps

On Mon, Sep 25, 2017 at 04:23:30PM +0530, Vidya Srinivas wrote: > From: Uma Shankar > > For certain platforms on certain encoders, timings are driven > from port instead of pipe. Thus, we can't rely on pipe scanline > registers to get the timing information. Some cases

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() URL : https://patchwork.freedesktop.org/series/30838/ State : failure == Summary == Series 30838v1 series starting with [1/3] drm/i915/execlists: Microoptimise

Re: [Intel-gfx] [PATCH] drm/i915: Don't rmw PIPESTAT enable bits

On Fri, Sep 15, 2017 at 01:03:36PM +0300, Ville Syrjälä wrote: > On Thu, Sep 14, 2017 at 09:37:37PM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2017-09-14 16:17:31) > > > From: Ville Syrjälä > > > > > > i830 seems to occasionally forget the PIPESTAT

Re: [Intel-gfx] [PATCH v2] drm/i915/bios: ignore HDMI on port A

On Thu, 21 Sep 2017, Ville Syrjälä wrote: > On Thu, Sep 21, 2017 at 05:19:20PM +0300, Jani Nikula wrote: >> The hardware state readout oopses after several warnings when trying to >> use HDMI on port A, if such a combination is configured in VBT. Filter >> the combo

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/5] drm/i915: Make own struct for execlist items

Patchwork writes: > == Series Details == > > Series: series starting with [CI,1/5] drm/i915: Make own struct for execlist > items > URL : https://patchwork.freedesktop.org/series/30761/ > State : warning > > == Summary == > > Series 30761v1 series starting

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Allow optimized platform checks

On 20/09/2017 10:56, Tvrtko Ursulin wrote: On 20/09/2017 10:39, Jani Nikula wrote: On Wed, 20 Sep 2017, Tvrtko Ursulin wrote: From: Tvrtko Ursulin If we store the platform as a bitmask, and convert the IS_PLATFORM macro to use it, we allow

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Sat, 23 Sep 2017, vathsala nagaraju wrote: > Add defines for dpcd register 2009 (synchronization latency > in sink). > > Cc: Rodrigo Vivi > CC: Puthikorn Voravootivat > Reviewed-by: Rodrigo Vivi

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

On Sat, 23 Sep 2017, vathsala nagaraju wrote: > Set frames before SU entry value for max resync frame count of > dpcd register 2009, bit field 0:3. > > v2 : > - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) > - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) > - add

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.

On 22/09/2017 21:12, Srivatsa, Anusha wrote: Sending to intel-gfx. -Original Message- From: Ursulin, Tvrtko Sent: Thursday, September 21, 2017 8:16 AM To: Srivatsa, Anusha ; intel- g...@lists.freedektop.org Cc: Chris Wilson ;

Re: [Intel-gfx] [PATCH i-g-t 2/2] igt_core: Rework igt_system()

On 09/21/2017 03:52 PM, Petri Latvala wrote: > Instead of redirecting output to pipes and forking, redirect after > forking to avoid having to carefully unredirect before logging > anything. > > igt@tools_test@sysfs_l3_parity had a racy condition where it prints > the output of intel_l3_parity

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_frontbuffer_tracking: Try harder to collect CRC's

On Fri, 2017-09-22 at 15:25 +, Rodrigo Vivi wrote: > > Maybe we are missing a vblank wait somewhere on kernel CRC code?! > Or maybe o kernel we read and discard the first for GLK?! :/ > Also this is pipe crc right?! Shouldn't it be independent of the > panel at the end?! Does it only happen

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value

On Mon, 2017-09-25 at 09:45 +, Michal Wajdeczko wrote: > By combining default value into helper macro we can initialize > modparams struct in the same automatic way as it was declared. > This will initialize members in the same order as declared > and additionally will disallow declaring new

Re: [Intel-gfx] [PATCH] drm/i915: Don't rmw PIPESTAT enable bits

On Thu, Sep 14, 2017 at 06:17:31PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > i830 seems to occasionally forget the PIPESTAT enable bits when > we read the register. These aren't the only registers on i830 that > have problems with RMW, as reading the

[Intel-gfx] [PATCH] drm/i915: Enable scanline read based on frame timestamps

From: Uma Shankar For certain platforms on certain encoders, timings are driven from port instead of pipe. Thus, we can't rely on pipe scanline registers to get the timing information. Some cases scanline register read will not be functional. This is causing vblank evasion

[Intel-gfx] [PATCH v2 1/3] drm/i915: Make I915_PARAMS_FOR_EACH macro more flexible

We should not add trailing ; after each member to allow other than statements-style uses of this helper macro. While here s/func/param for clarity. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Jani Nikula

[Intel-gfx] [PATCH v2 3/3] drm/i915: Fix default values of some modparams

Members should be initialized with values of matching types. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Jani Nikula Cc: Joonas Lahtinen Reviewed-by: Chris Wilson

[Intel-gfx] [PATCH v2 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value

By combining default value into helper macro we can initialize modparams struct in the same automatic way as it was declared. This will initialize members in the same order as declared and additionally will disallow declaring new member without proper default value for it. v2: make MEMBER macro

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Extend I915_PARAMS_FOR_EACH with default member value

On Mon, 25 Sep 2017, Michal Wajdeczko wrote: > By combining default value into helper macro we can initialize > modparams struct in the same automatic way as it was declared. > This will initialize members in the same order as declared > and additionally will disallow

Re: [Intel-gfx] [PATCH i-g-t 4/7] intel-gpu-overlay: Catch-up to new i915 PMU

Quoting Tvrtko Ursulin (2017-09-25 16:14:59) > From: Tvrtko Ursulin > > Signed-off-by: Tvrtko Ursulin > --- > lib/igt_perf.h | 93 > ++-- > overlay/gem-interrupts.c | 2 +- >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() (rev2)

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() (rev2) URL : https://patchwork.freedesktop.org/series/30838/ State : success == Summary == Series 30838v2 series starting with [1/3] drm/i915/execlists: Microoptimise

[Intel-gfx] [PATCH 6/8] drm/i915: Engine busy time tracking

From: Tvrtko Ursulin Track total time requests have been executing on the hardware. We add new kernel API to allow software tracking of time GPU engines are spending executing requests. Both per-engine and global API is added with the latter also being exported for

[Intel-gfx] [PATCH 3/8] drm/i915/pmu: Expose a PMU interface for perf queries

From: Tvrtko Ursulin From: Chris Wilson From: Tvrtko Ursulin From: Dmitry Rogozhkin The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll

[Intel-gfx] [PATCH 8/8] drm/i915: Gate engine stats collection with a static key

From: Tvrtko Ursulin This reduces the cost of the software engine busyness tracking to a single no-op instruction when there are no listeners. v2: Rebase and some comments. v3: Rebase. v4: Checkpatch fixes. v5: Rebase. v6: Use system_long_wq to avoid being blocked by

[Intel-gfx] [PATCH 4/8] drm/i915/pmu: Suspend sampling when GPU is idle

From: Tvrtko Ursulin If only a subset of events is enabled we can afford to suspend the sampling timer when the GPU is idle and so save some cycles and power. v2: Rebase and limit timer even more. v3: Rebase. v4: Rebase. v5: Skip action if perf PMU failed to register.

[Intel-gfx] [PATCH 1/8] drm/i915: Convert intel_rc6_residency_us to ns

From: Tvrtko Ursulin Will be used for exposing the PMU counters. v2: * Move intel_runtime_pm_get/put to the callers. (Chris Wilson) * Restore full unit conversion precision. Signed-off-by: Tvrtko Ursulin ---

[Intel-gfx] [PATCH v5 0/8] i915 PMU and engine busy stats

From: Tvrtko Ursulin Fifth spin of the i915 PMU series. Just some small cleanups across a few patches and a rebase to latest drm-tip. Patches 1-2 are small refactors to make the following work easier. Patch 3 is the main bit. Patch 4 is a small optimisation on top,

[Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU

From: Tvrtko Ursulin We can use engine busy stats instead of the MMIO sampling timer for better efficiency. As minimum this saves period * num_engines / sec mmio reads, and in a better case, when only engine busy samplers are active, it enables us to not kick off the

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Introduce a preempt context

On Mon, Sep 25, 2017 at 12:44:07PM +0100, Chris Wilson wrote: > Add another perma-pinned context for using for preemption at any time. > We cannot just reuse the existing kernel context, as first and foremost > we need to ensure that we can preempt the kernel context itself, so > require a

[Intel-gfx] [PATCH 2/8] drm/i915: Extract intel_get_cagf

From: Tvrtko Ursulin Code to be shared between debugfs and the PMU implementation. v2: Checkpatch cleanup. v3: Also consolidate i915_sysfs.c/gt_act_freq_mhz_show. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson

[Intel-gfx] [PATCH 5/8] drm/i915: Wrap context schedule notification

From: Tvrtko Ursulin No functional change just something which will be handy in the following patch. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_lrc.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-)

[Intel-gfx] ✗ Fi.CI.IGT: warning for igt_command_line.sh: Fix bashism

== Series Details == Series: igt_command_line.sh: Fix bashism URL : https://patchwork.freedesktop.org/series/30826/ State : warning == Summary == Test prime_mmap: Subgroup test_userptr: dmesg-warn -> PASS (shard-hsw) fdo#102939 Test perf: Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for IGT PMU support (rev4)

== Series Details == Series: IGT PMU support (rev4) URL : https://patchwork.freedesktop.org/series/28253/ State : success == Summary == IGT patchset tested on top of latest successful build c117213c06d0f47937c1f225ebead5e1fe8c7a0e igt/gem_exec_whisper: Smoketest context priorities with

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable scanline read based on frame timestamps

Hi, Ville, trybot also passed for DSI system again : https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_1193/ It did some GEM code on BDW that Vidya can comment but should not be related to this patch. Are we good to merge now, finally and get this machine also back to normal pool? Br, Jani >

Re: [Intel-gfx] [PATCH i-g-t 6/7] gem_wsim: Busy stats balancers

Quoting Tvrtko Ursulin (2017-09-25 16:15:01) > From: Tvrtko Ursulin > > Add busy and busy-avg balancers which make balancing > decisions by looking at engine busyness via the i915 PMU. "And thus are able to make decisions on the actual instantaneous load of the system,

[Intel-gfx] [PATCH i-g-t 3/7] intel-gpu-overlay: Fix interrupts PMU readout

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- overlay/gem-interrupts.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c index a84aef0398a7..3eda24f4d7eb

[Intel-gfx] [PATCH i-g-t 6/7] gem_wsim: Busy stats balancers

From: Tvrtko Ursulin Add busy and busy-avg balancers which make balancing decisions by looking at engine busyness via the i915 PMU. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 140

[Intel-gfx] [PATCH i-g-t 5/7] tests/perf_pmu: Tests for i915 PMU API

From: Tvrtko Ursulin A bunch of tests for the new i915 PMU feature. Parts of the code were initialy sketched by Dmitry Rogozhkin. v2: (Most suggestions by Chris Wilson) * Add new class/instance based engine list. * Add gem_has_engine/gem_require_engine to work with

[Intel-gfx] [PATCH i-g-t 2/7] intel-gpu-overlay: Consolidate perf PMU access to library

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- lib/igt_perf.c | 33 + lib/igt_perf.h | 2 ++ overlay/gem-interrupts.c | 16 +--- overlay/gpu-freq.c | 22

[Intel-gfx] [PATCH i-g-t 7/7] media-bench.pl: Add busy balancers to the list

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- scripts/media-bench.pl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/scripts/media-bench.pl b/scripts/media-bench.pl index 0956ef0a0621..78f45199e95d 100755 ---

[Intel-gfx] [PATCH i-g-t 4/7] intel-gpu-overlay: Catch-up to new i915 PMU

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- lib/igt_perf.h | 93 ++-- overlay/gem-interrupts.c | 2 +- overlay/gpu-freq.c | 4 +-- overlay/gpu-top.c| 68

[Intel-gfx] [PATCH i-g-t 1/7] intel-gpu-overlay: Move local perf implementation to a library

From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- lib/Makefile.sources | 2 ++ overlay/perf.c => lib/igt_perf.c | 2 +- overlay/perf.h => lib/igt_perf.h | 2 ++ overlay/Makefile.am | 6 ++

[Intel-gfx] [PATCH i-g-t v2 0/7] IGT PMU support

From: Tvrtko Ursulin 1. Fixes for intel-gpu-overlay to work on top of the proposed i915 PMU perf API. 2. New test to exercise the same API. 3. Update to gem_wsim and media-bench.pl to be able to use engine busyness via PMU for making balancing decisions. v2: * Added

Re: [Intel-gfx] [PATCH i-g-t 5/7] tests/perf_pmu: Tests for i915 PMU API

Quoting Tvrtko Ursulin (2017-09-25 16:15:00) > From: Tvrtko Ursulin > > A bunch of tests for the new i915 PMU feature. > > Parts of the code were initialy sketched by Dmitry Rogozhkin. > > v2: (Most suggestions by Chris Wilson) > * Add new class/instance based engine

Re: [Intel-gfx] [PATCH i-g-t 1/7] intel-gpu-overlay: Move local perf implementation to a library

Quoting Tvrtko Ursulin (2017-09-25 16:14:56) > From: Tvrtko Ursulin > > Signed-off-by: Tvrtko Ursulin > --- > lib/Makefile.sources | 2 ++ > overlay/perf.c => lib/igt_perf.c | 2 +- > overlay/perf.h => lib/igt_perf.h | 2 ++ >

Re: [Intel-gfx] [PATCH i-g-t 2/7] intel-gpu-overlay: Consolidate perf PMU access to library

Quoting Tvrtko Ursulin (2017-09-25 16:14:57) > From: Tvrtko Ursulin > > Signed-off-by: Tvrtko Ursulin > --- > lib/igt_perf.c | 33 + > lib/igt_perf.h | 2 ++ > overlay/gem-interrupts.c | 16

[Intel-gfx] ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev12)

== Series Details == Series: i915 PMU and engine busy stats (rev12) URL : https://patchwork.freedesktop.org/series/27488/ State : success == Summary == Series 27488v12 i915 PMU and engine busy stats https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/12/mbox/ Test

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

== Series Details == Series: series starting with [1/7] drm/i915/execlists: Microoptimise execlists_cancel_port_request() URL : https://patchwork.freedesktop.org/series/30834/ State : failure == Summary == Test perf: Subgroup polling: fail -> PASS

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

On Mon, Sep 25, 2017 at 09:10:28AM +, vathsala nagaraju wrote: > On Monday 25 September 2017 02:00 PM, Jani Nikula wrote: > > On Sat, 23 Sep 2017, vathsala nagaraju > wrote: > > Set frames before SU entry value for max resync frame count of >

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Convert intel_rc6_residency_us to ns

Quoting Tvrtko Ursulin (2017-09-25 16:15:36) > From: Tvrtko Ursulin > > Will be used for exposing the PMU counters. > > v2: > * Move intel_runtime_pm_get/put to the callers. (Chris Wilson) > * Restore full unit conversion precision. > > Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable scanline read based on frame timestamps

HI, > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > Of Saarinen, Jani > Sent: maanantai 25. syyskuuta 2017 19.34 > To: intel-gfx@lists.freedesktop.org; Srinivas, Vidya > ; Ville Syrjälä

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Engine busy time tracking

Quoting Tvrtko Ursulin (2017-09-25 16:15:41) > From: Tvrtko Ursulin > > Track total time requests have been executing on the hardware. > > We add new kernel API to allow software tracking of time GPU > engines are spending executing requests. > > Both per-engine and

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Gate engine stats collection with a static key

Quoting Tvrtko Ursulin (2017-09-25 16:15:43) > From: Tvrtko Ursulin > > This reduces the cost of the software engine busyness tracking > to a single no-op instruction when there are no listeners. > > v2: Rebase and some comments. > v3: Rebase. > v4: Checkpatch fixes. >

Re: [Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU

Quoting Tvrtko Ursulin (2017-09-25 16:15:42) > From: Tvrtko Ursulin > > We can use engine busy stats instead of the MMIO sampling timer > for better efficiency. > > As minimum this saves period * num_engines / sec mmio reads, > and in a better case, when only engine

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request()

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Microoptimise execlists_cancel_port_request() URL : https://patchwork.freedesktop.org/series/30838/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS

Re: [Intel-gfx] [PATCH 02/21] drm/i915: introduce simple gemfs

Quoting Matthew Auld (2017-09-22 18:32:33) > @@ -4914,6 +4938,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) > > spin_lock_init(_priv->fb_tracking.lock); > > + WARN_ON(i915_gemfs_init(dev_priv)); Make this kinder, the driver will happily continue without a special

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Introduce a preempt context

Quoting Michał Winiarski (2017-09-25 16:16:33) > On Mon, Sep 25, 2017 at 12:44:07PM +0100, Chris Wilson wrote: > > Add another perma-pinned context for using for preemption at any time. > > We cannot just reuse the existing kernel context, as first and foremost > > we need to ensure that we can

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Mon, Sep 25, 2017 at 09:01:38AM +, vathsala nagaraju wrote: > On Monday 25 September 2017 01:53 PM, Jani Nikula wrote: > > On Sat, 23 Sep 2017, vathsala nagaraju > wrote: > > Add defines for dpcd register 2009 (synchronization latency >

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