On Mon, Jan 22, 2018 at 12:55:00PM -0500, Sean Paul wrote:
> The commit below returned earlier than before, but failed to move the
> info message when authenticating without downstream devices. This patch
> restores the message on authentication success.
>
> Fixes: 87eb3ec818fa ("drm/i915: II stag
On Mon, 29 Jan 2018, Jani Nikula wrote:
> On Mon, 29 Jan 2018, Lionel Landwerlin wrote:
>> On 29/01/18 09:02, Chris Wilson wrote:
>>> Quoting Lionel Landwerlin (2018-01-29 08:33:46)
This reverts commit 5b54eddd3920e9f6f1a6d972454baf350cbae77e.
Conflicts:
drivers/gpu
Quoting Daniele Ceraolo Spurio (2018-01-30 00:24:04)
>
>
> > @@ -979,17 +979,19 @@ static int guc_clients_create(struct intel_guc *guc)
> > }
> > guc->execbuf_client = client;
> >
> > - client = guc_client_alloc(dev_priv,
> > - INTEL_INFO(dev_priv)
Quoting Rodrigo Vivi (2018-01-29 21:40:27)
> On Mon, Jan 29, 2018 at 08:45:24PM +, Chris Wilson wrote:
> > Quoting Srivatsa, Anusha (2018-01-29 20:17:25)
> > >
> > >
> > > >-Original Message-
> > > >From: Vivi, Rodrigo
> > > >Sent: Friday, January 26, 2018 10:22 AM
> > > >To: intel-gf
On 1/29/2018 10:01 PM, Lionel Landwerlin wrote:
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregat
Use debugobjects to track and validate the lifecycle of a struct
drm_i915_gem_request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 14
drivers/gpu/drm/i915/i915_gem_request.c | 140 ++--
drivers/gpu/drm/i915/i915_gem_request.h | 32
From: "Kumar, Mahesh"
Platforms before Gen11 were sharing lanes between port-A & port-E.
This limitation is no more there.
Changes since V1:
- optimize the code (Shashank/Jani)
- create helper function to get max lanes (ville)
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/intel_ddi.c
On Monday 22 January 2018 11:25 PM, Sean Paul wrote:
The commit below returned earlier than before, but failed to move the
info message when authenticating without downstream devices. This patch
restores the message on authentication success.
Fixes: 87eb3ec818fa ("drm/i915: II stage HDCP auth
This patch adds support for YCBCR 4:4:4 CRTC output format.
To do this, this patch extends the existing YCBCR 4:2:0
framework by:
- Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
- Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
- Adding necessary checks in modeset se
This patch series adds YCBCR 4:2:0 output support for LSPCON displays.
In order to indicate the color format of output, to the LSPCON device,
a source has to set and send proper AVI infoframes to LSPCON. So this
patch series:
- first adds AVI infoframes support for LSPCON
- then adds YCBCR 4:2:0 ou
From: "Sharma, Shashank"
Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR formats, we will need more such flags.
The idea behind this patch is to replace this bool with an enum,
and plu
From: "Sharma, Shashank"
Different LSPCON vendors specify their custom methods to pass
AVI infoframes to the LSPCON chip, so does Parade tech.
This patch adds functions to arrange and write AVI infoframes
into Parade LSPCON chips.
V2: rebase
V3: Added r-b from Maarten
Cc: Imre Deak
Cc: Ville
From: "Sharma, Shashank"
Intel LSPCON chip is provided by 2 vendors:
- Megachips America (MCA)
- Parade technologies (Parade tech)
Its important to know the vendor of this chip, as the address to
write AVI infoframes is different for those two.
This patch reads the vendor OUI signature, and mar
From: "Sharma, Shashank"
In order to pass AVI infoframes to LSPCON devices, a source has to
write them in a vendor recommended method and location.
This patch series:
- adds generic LSPCON infoframe setup functions.
- registers these functions into existing AVI infoframe framework.
- triggers th
From: "Sharma, Shashank"
As LSPCON is a DP branch device, LSPCON vendors define
specific methods to pass AVI infoframes to the the chip.
This patch adds:
- a generic wrapper function for writing AVI infoframes for
all LSPCON devices.
- a vendor specific function to wrire AVI infoframes into
M
From: "Sharma, Shashank"
LSPCON chips can generate YCBCR outputs, if asked nicely :).
In order to generate YCBCR 4:2:0 outputs, a source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:2:0 in AVI infoframes
Whereas for YCBCR 4:4:4 outputs, the source must:
- send YCBCR 4:4
Adding a shared fence to a reservation_object is currently split into
two handlers, one to insert the fence into the existing array and the
other to replace the existing array with a new larger array. The first
step in both of these routines involves scanning the existing array to
decide if it can
Op 30-01-18 om 07:16 schreef Kumar, Mahesh:
> Hi,
>
> On 1/30/2018 9:35 AM, Srinivas, Vidya wrote:
>>
>>> -Original Message-
>>> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>>> Sent: Monday, January 29, 2018 10:47 PM
>>> To: Srinivas, Vidya ; intel-
>>> g...@lists.fre
Thanks Sagar, fixed locally.
On 30/01/18 09:08, Sagar Arun Kamble wrote:
On 1/29/2018 10:01 PM, Lionel Landwerlin wrote:
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a
On Tue, 30 Jan 2018, Shashank Sharma wrote:
> From: "Sharma, Shashank"
>
> Currently, we are using a bool in CRTC state (state->ycbcr420),
> to indicate modeset, that the output format is YCBCR 4:2:0. Now in
> order to support other YCBCR formats, we will need more such flags.
>
> The idea behind
Op 29-01-18 om 16:41 schreef Leo Li:
> Updated IGT results seem sane:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7698/shards.html
>
> Would someone be able to apply this patch?
>
Thanks for the reminder, pushed.
~Maarten
___
Intel-gfx mailing l
On 27/01/2018 09:05, Jani Nikula wrote:
On Fri, 26 Jan 2018, Rodrigo Vivi wrote:
On Fri, Jan 26, 2018 at 10:12:00AM +, Jani Nikula wrote:
On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
The only difference is that this SKUs has the full
Port A/E split named as Port F.
But since SKUs differenc
On 26/01/2018 13:10, Michal Wajdeczko wrote:
On Wed, 24 Jan 2018 17:18:18 +0100, Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Define DRM_LOG_NAME to i915 so that the log messages we output change
from:
[drm] RC6 on
to:
[i915] RC6 on
Signed-off-by: Tvrtko Ursulin
Cc: dri-de...@lists.fr
Dynamic Refresh Rate Switch(DRRS) is used to switch the panel's
refresh rate to the lowest vrefresh supported by panel, when frame is
not flipped for more than a Sec.
In kernel, DRRS uses the front buffer tracking infrastructure.
Hence DRRS test coverage is added along with other frontbuffer track
On Tue, Jan 30, 2018 at 09:02:45AM +, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2018-01-30 00:24:04)
> >
> >
> > > @@ -979,17 +979,19 @@ static int guc_clients_create(struct intel_guc *guc)
> > > }
> > > guc->execbuf_client = client;
> > >
> > > - client = guc_c
These two functions are very similar so simplify things by removing the
duplication.
Add a seperate sleeping poll timeout parameter, useful for longer polls
like the CDCLK change on BXT/GLK. The next patch will take that into use.
While at it document snb_pcode_request() and clean up a bit the
er
Currently we see sporadic timeouts during CDCLK changing both on BXT and
GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
changing the frequency in a tight loop after blanking the display. The
upper bound for the completion time is 800us based on my tests, so
increase it from
There is no requirement for doing the PCODE request polling atomically,
so do that only for a short time switching to sleeping poll afterwards.
The specification requires a 150usec timeout for the change notification,
so let's use that for the atomic poll. Do the extra 2ms poll - needed as
a workar
Quoting Michał Winiarski (2018-01-30 11:25:50)
> On Tue, Jan 30, 2018 at 09:02:45AM +, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2018-01-30 00:24:04)
> > >
> > >
> > > > @@ -979,17 +979,19 @@ static int guc_clients_create(struct intel_guc
> > > > *guc)
> > > > }
> > > >
Quoting Imre Deak (2018-01-30 11:47:11)
> These two functions are very similar so simplify things by removing the
> duplication.
>
> Add a seperate sleeping poll timeout parameter, useful for longer polls
> like the CDCLK change on BXT/GLK. The next patch will take that into use.
>
> While at it
Quoting Imre Deak (2018-01-30 11:47:10)
> Currently we see sporadic timeouts during CDCLK changing both on BXT and
> GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> changing the frequency in a tight loop after blanking the display. The
> upper bound for the completion time
Don't just wait for the batch to be completed, wait for the system to
idle! Then wake it up and do it again.
Signed-off-by: Chris Wilson
---
tests/gem_sync.c | 41 +
1 file changed, 41 insertions(+)
diff --git a/tests/gem_sync.c b/tests/gem_sync.c
index e
Chris Wilson writes:
> Previously, we relied on only running the hangcheck while somebody was
> waiting on the GPU, in order to minimise the amount of time hangcheck
> had to run. (If nobody was watching the GPU, nobody would notice if the
> GPU wasn't responding -- eventually somebody would care
Quoting Mika Kuoppala (2018-01-30 12:18:17)
> Chris Wilson writes:
>
> > Previously, we relied on only running the hangcheck while somebody was
> > waiting on the GPU, in order to minimise the amount of time hangcheck
> > had to run. (If nobody was watching the GPU, nobody would notice if the
> >
== Series Details ==
Series: drm/i915: Enable debugobjects for request validation (rev3)
URL : https://patchwork.freedesktop.org/series/37240/
State : success
== Summary ==
Series 37240v3 drm/i915: Enable debugobjects for request validation
https://patchwork.freedesktop.org/api/1.0/series/3724
On Tue, Jan 30, 2018 at 11:57:49AM +, Chris Wilson wrote:
> Quoting Imre Deak (2018-01-30 11:47:11)
> > These two functions are very similar so simplify things by removing the
> > duplication.
> >
> > Add a seperate sleeping poll timeout parameter, useful for longer polls
> > like the CDCLK ch
Am 30.01.2018 um 10:32 schrieb Chris Wilson:
Adding a shared fence to a reservation_object is currently split into
two handlers, one to insert the fence into the existing array and the
other to replace the existing array with a new larger array. The first
step in both of these routines involves s
Quoting Imre Deak (2018-01-30 12:25:39)
> On Tue, Jan 30, 2018 at 11:57:49AM +, Chris Wilson wrote:
> > Quoting Imre Deak (2018-01-30 11:47:11)
> > > These two functions are very similar so simplify things by removing the
> > > duplication.
> > >
> > > Add a seperate sleeping poll timeout para
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-01-30 12:18:17)
>> Chris Wilson writes:
>>
>> > Previously, we relied on only running the hangcheck while somebody was
>> > waiting on the GPU, in order to minimise the amount of time hangcheck
>> > had to run. (If nobody was watching the GPU,
Am 30.01.2018 um 13:50 schrieb Chris Wilson:
Quoting Christian König (2018-01-30 12:26:05)
Am 30.01.2018 um 10:32 schrieb Chris Wilson:
Adding a shared fence to a reservation_object is currently split into
two handlers, one to insert the fence into the existing array and the
other to replace th
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/r
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)
URL : https://patchwork.freedesktop.org/series/36068/
State : warning
== Summary ==
Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/2/mbox
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()
https://patchwork.freedesktop.org/api/1.0/series/373
On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote:
> Currently we see sporadic timeouts during CDCLK changing both on BXT and
> GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> changing the frequency in a tight loop after blanking the display. The
> upper bound for
From: Mahesh Kumar
GEN9 onwards bypass path allocation of 4 blocks was needed, as per
hardware design. ICL doesn't require bypass path allocation of 4 DDB
blocks, handling the same in this patch.
v2 (from Paulo):
- No need for a comment that says what the code already says.
Reviewed-by: Paulo
These patches were part of the other ICL series that arrived on the
list a few days ago, they already received public reviews. They should
be good to go, but let's see what the CI system has to say about them
first.
James Ausmus (1):
drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Kelvin G
From: Mahesh Kumar
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
fixed number anymore in GEN11, it varies according to bits per pixel
and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
size = 512
This patch addresses the same.
v2 (from Paulo):
- Make it co
From: Kelvin Gardiner
This patch clears a single bit. The bit is 0 by default but expected
not to be set. Explicitly clearing the bit in this patch is intended
to indicate some thinking has occurred, and that we want this bit
cleared and we are not just excepting the default value.
We also stop
From: Mahesh Kumar
This patch introduce MBus control registers and their bit-fields
MBUS_ABOX_CTL
MBUS_BBOX_CTL
MBUS_DBOX_CTL
MBUS_UBOX_CTL
Changes Since V1:
- Use function like macros (Paulo)
- fix copy-paste error (Paulo)
Reviewed-by: Paulo Zanoni
Reviewed-by: James Ausmus
Signed-off-by:
From: Mahesh Kumar
ICL require DDB allocation of plane to be more than "minimum display
buffer needed" for each level in order to enable WM level.
This patch implements and consider the same while allocating DDB
and enabling WM.
Changes Since V1:
- rebase
Changes Since V2:
- Remove extra pare
From: Mahesh Kumar
We don't have planar pixel format support implemented for ICL yet.
ICL require 2 display planes to be allocated for Planar formats unlike
previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in
From: James Ausmus
ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.
v2: No changes
v3:
It's 10us for gen 11.
Reviewed-by: Mahesh Kumar
Reviewed-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 766f4fdd
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the CNL patch by Nanley Chery.
v2: Rebase.
Cc: Anuj Phogat
Cc: Nanley Chery
Cc: Rodrigo Vivi
Requested-by: Anuj Phogat
Tested-by: Anuj Phogat
Reviewed-by: Rodrigo Vivi
According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7, so correctly apply the check there.
This is required to make NV12 work.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()
https://patchwork.freedesktop.org/api/1.0/series/373
== Series Details ==
Series: drm/i915: Enable debugobjects for request validation (rev3)
URL : https://patchwork.freedesktop.org/series/37240/
State : failure
== Summary ==
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Subgrou
On Tue, Jan 30, 2018 at 02:54:11PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7, so correctly apply the check there.
The register still has only 5 bits for the line watermark. However the
spec says "Hardware ignores the l
On Tue, Jan 30, 2018 at 03:42:45PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote:
> > Currently we see sporadic timeouts during CDCLK changing both on BXT and
> > GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> > changing the frequ
On Tue, Jan 30, 2018 at 09:35:34AM +0100, Daniel Vetter wrote:
> On Mon, Jan 22, 2018 at 12:55:00PM -0500, Sean Paul wrote:
> > The commit below returned earlier than before, but failed to move the
> > info message when authenticating without downstream devices. This patch
> > restores the message
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)
URL : https://patchwork.freedesktop.org/series/36068/
State : failure
== Summary ==
Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON
https://patchwork.freedesktop.org/api/1.0/series/36068/revisions/2/mbox
Currently we see sporadic timeouts during CDCLK changing both on BXT and
GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
changing the frequency in a tight loop after blanking the display. The
upper bound for the completion time is 800us based on my tests, so
increase it from
The commit below returned earlier than before, but failed to move the
info message when authenticating without downstream devices. This patch
restores the message on authentication success.
Changes in v2:
- s/no downstream devices/no repeater present/ (Ram)
Fixes: 87eb3ec818fa ("drm/i915: II stag
There is no requirement for doing the PCODE request polling atomically,
so do that only for a short time switching to sleeping poll afterwards.
The specification requires a 150usec timeout for the change notification,
so let's use that for the atomic poll. Do the extra 2ms poll - needed as
a workar
HDCP was a bit too chatty to get along with the rest of the i915 driver.
Suggested-by: Daniel Vetter
Signed-off-by: Sean Paul
---
drivers/gpu/drm/i915/intel_hdcp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i
On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote:
>
> Thanks all,
>
> I don't really read much opposition to the current patch series. If
> anything we could actually want to do more it seems.
> It would be good to have the green light and land that.
> I've played quickly with a Chris'
According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7.
For level 0 the number of lines is ignored, so always write 0 there
to prevent overflowing the 5 bits value.
This is required to make NV12 work.
Signed-off-by: Maarten Lankhorst
Cc: Ville Syrjälä
---
driver
On Tue, Jan 16, 2018 at 02:05:30PM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915: Add display WA #1175 for
> planes ending close to right screen edge
> URL : https://patchwork.freedesktop.org/series/36526/
> State : failure
The failures look
From: Johnson Lin
Some panels support limited range output (16-235) compared
to full range RGB values (0-255). Also userspace can control
the RGB range using "Broadcast RGB" property. Currently the
code to handle full range to limited range is broken. This
patch fixes the same by properly scaling
On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote:
> HDCP was a bit too chatty to get along with the rest of the i915 driver.
>
> Suggested-by: Daniel Vetter
> Signed-off-by: Sean Paul
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 9 +
> 1 file change
On Tue, Jan 30, 2018 at 04:05:20PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7.
>
> For level 0 the number of lines is ignored, so always write 0 there
> to prevent overflowing the 5 bits value.
>
> This is required to
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_sysfs_edid_timing:
On Tue, Jan 30, 2018 at 08:49:22PM +0530, Uma Shankar wrote:
> From: Johnson Lin
>
> Some panels support limited range output (16-235) compared
> to full range RGB values (0-255). Also userspace can control
> the RGB range using "Broadcast RGB" property. Currently the
> code to handle full range
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, December 22, 2017 9:43 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited R
Quoting Imre Deak (2018-01-30 14:29:39)
> There is no requirement for doing the PCODE request polling atomically,
> so do that only for a short time switching to sleeping poll afterwards.
> The specification requires a 150usec timeout for the change notification,
> so let's use that for the atomic
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_flip:
Subgroup wf_vb
From: Johnson Lin
Some panels support limited range output (16-235) compared
to full range RGB values (0-255). Also userspace can control
the RGB range using "Broadcast RGB" property. Currently the
code to handle full range to limited range is broken. This
patch fixes the same by properly scaling
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, January 30, 2018 8:53 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v3] drm/i915: Fix Limited Rang
Although this is a debugfs routine, so it may seem a little pointless to
optimize, it is heavily used by igt to idle the driver and HW between
every test. As such, speeding it from 40ms to 40us on a plain Broadwell
system is beneficial overall.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: J
On 30/01/18 15:01, Lahtinen, Joonas wrote:
On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote:
Thanks all,
I don't really read much opposition to the current patch series. If
anything we could actually want to do more it seems.
It would be good to have the green light and land that.
I'v
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/r
Quoting Mika Kuoppala (2018-01-30 13:00:50)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2018-01-30 12:18:17)
> >> Chris Wilson writes:
> >>
> >> > Previously, we relied on only running the hangcheck while somebody was
> >> > waiting on the GPU, in order to minimise the amount of time ha
On Tue, Jan 30, 2018 at 04:12:14PM +0100, Daniel Vetter wrote:
> On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote:
> > HDCP was a bit too chatty to get along with the rest of the i915 driver.
> >
> > Suggested-by: Daniel Vetter
> > Signed-off-by: Sean Paul
>
> Reviewed-by: Daniel Vette
On Tue, Jan 30, 2018 at 09:29:34AM -0500, Sean Paul wrote:
> The commit below returned earlier than before, but failed to move the
> info message when authenticating without downstream devices. This patch
> restores the message on authentication success.
>
> Changes in v2:
> - s/no downstream devi
== Series Details ==
Series: dma-buf: Refanctor reservation_object_add_shared_fence()
URL : https://patchwork.freedesktop.org/series/37327/
State : success
== Summary ==
Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON
format
Test kms_flip:
Subgroup wf_vb
This is a precautionary measure as I have no evidence to suggest we've
hit a bug here (I was hoping this might explain gdg's odd behaviour, but
alas), but given that we have a function to flush the ggtt writes it
seems prudent to use it prior to changing the fence register. Due to the
intrinsic nat
== Series Details ==
Series: drm/i915: Enable debugobjects for request validation (rev3)
URL : https://patchwork.freedesktop.org/series/37240/
State : success
== Summary ==
Series 37240v3 drm/i915: Enable debugobjects for request validation
https://patchwork.freedesktop.org/api/1.0/series/3724
Regards
Shashank
On 1/30/2018 3:53 PM, Jani Nikula wrote:
On Tue, 30 Jan 2018, Shashank Sharma wrote:
From: "Sharma, Shashank"
Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR for
== Series Details ==
Series: series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts
during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37338/
State : success
== Summary ==
Series 37338v1 series starting with [1/3] drm/i915/bxt, glk: Increase PCODE
timeou
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation.
URL : https://patchwork.freedesktop.org/series/37325/
State : warning
== Summary ==
Test perf:
Subgroup enable-disable:
fail -> PASS (shard-apl) fdo#103715
Subgroup b
== Series Details ==
Series: ICL mergeable patches
URL : https://patchwork.freedesktop.org/series/37341/
State : success
== Summary ==
Series 37341v1 ICL mergeable patches
https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_ent
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE
timeouts during CDCLK freq changing
URL : https://patchwork.freedesktop.org/series/37344/
State : success
== Summary ==
Series 37344v1 series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE
== Series Details ==
Series: drm/i915: Restore HDCP DRM_INFO when with no downstream (rev2)
URL : https://patchwork.freedesktop.org/series/36921/
State : failure
== Summary ==
Applying: drm/i915: Restore HDCP DRM_INFO when with no downstream
error: Failed to merge in the changes.
Using index i
== Series Details ==
Series: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS
URL : https://patchwork.freedesktop.org/series/37345/
State : failure
== Summary ==
Applying: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS
Using index info to reconstruct a base tree...
M drivers/gp
== Series Details ==
Series: drm/i915: Use the correct maximum in skl_compute_plane_wm (rev2)
URL : https://patchwork.freedesktop.org/series/37342/
State : failure
== Summary ==
Applying: drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm
error: sha1 information is lacking or u
A known issue that ring frequency transition would lead to
a full system stall had impacted the media performance when
the GT frequency is lower than IA freqency and there's heavy
GT workload while having low IA workload. In this case, the
ring frequency will be toggled between GT and IA frequency.
== Series Details ==
Series: drm/i915: Fix Limited Range Color Handling (rev4)
URL : https://patchwork.freedesktop.org/series/35725/
State : success
== Summary ==
Series 35725v4 drm/i915: Fix Limited Range Color Handling
https://patchwork.freedesktop.org/api/1.0/series/35725/revisions/4/mbox/
On 2018-01-27 21:28, Chris Wilson wrote:
If we remove some hardcoded assumptions about the preempt context having
a fixed id, reserved from use by normal user contexts, we may only
allocate the i915_gem_context when required. Then the subsequent
decisions on using preemption reduce to having th
Quoting Lis, Tomasz (2018-01-30 18:47:55)
>
>
> On 2018-01-27 21:28, Chris Wilson wrote:
> > If we remove some hardcoded assumptions about the preempt context having
> > a fixed id, reserved from use by normal user contexts, we may only
> > allocate the i915_gem_context when required. Then the su
== Series Details ==
Series: drm/i915: Optimize drop-caches
URL : https://patchwork.freedesktop.org/series/37351/
State : success
== Summary ==
Series 37351v1 drm/i915: Optimize drop-caches
https://patchwork.freedesktop.org/api/1.0/series/37351/revisions/1/mbox/
Test debugfs_test:
Sub
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