[Intel-gfx] [CI] drm/i915/icl: Prepare for more rings

From: Tvrtko Ursulin Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be

Re: [Intel-gfx] [PATCH v2] RFC drm/i915: Only acquire vblank-irq when waiting for vblank evade

On Mon, Feb 12, 2018 at 10:21:11PM +, Chris Wilson wrote: > Cc: Ville Syrjälä > Cc: Maarten Lankhorst > --- > drivers/gpu/drm/i915/intel_sprite.c | 65 > ++--- > 1 file changed, 38

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On 2/13/2018 6:17 PM, Chris Wilson wrote: Quoting Kumar, Abhijeet (2018-02-13 12:41:42) On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote: From: Abhijeet Kumar Finite loop and msleep was causing few igt@pm_rpm tests failure for HSW and BDW. Thus

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] lib/igt_kms.c: modify kmstest_dump_mode to print aspect ratio of a mode

Hi Mika, Thanks for the review. Please find my comments inline: On 2/12/2018 8:04 PM, Kahola, Mika wrote: On Wed, 2018-01-24 at 18:20 +0530, Nautiyal, Ankit K wrote: From: Ankit Nautiyal This patch adds the support to print the aspect ratio of the modes (if

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Tue, Feb 13, 2018 at 10:55:06AM +, Liviu Dudau wrote: > On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > > DRM drivers poll connectors in 10 sec intervals. The poll worker is > > stopped on ->runtime_suspend with cancel_delayed_work_sync(). However > > the poll worker

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On Tue, 13 Feb 2018, abhijeet.ku...@intel.com wrote: > From: Abhijeet Kumar > > Finite loop and msleep was causing few igt@pm_rpm tests failure > for HSW and BDW. Thus removing them. > > Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to >

Re: [Intel-gfx] [PATCH] drm/i915: Release the atomic kmap relocation cache around snb GTT w/a

On 12/02/2018 21:11, Chris Wilson wrote: When we need to rebind the vma into the global GTT for snb, we need to drop the current reloc_cache as it will be holding a kmap_atomic() and we may need to sleep for i915_vma_bind(). In practice, this is not an issue as we already hold an rpm reference

Re: [Intel-gfx] [PATCH] drm/i915: Release the atomic kmap relocation cache around snb GTT w/a

Quoting Tvrtko Ursulin (2018-02-13 13:42:03) > > On 12/02/2018 21:11, Chris Wilson wrote: > > When we need to rebind the vma into the global GTT for snb, we need to > > drop the current reloc_cache as it will be holding a kmap_atomic() and > > we may need to sleep for i915_vma_bind(). In

Re: [Intel-gfx] [PATCH] drm: Use idr_init_base(1) when using id==0 for invalid

Am 12.02.2018 um 18:14 schrieb Ville Syrjälä: On Mon, Feb 12, 2018 at 02:55:33PM +, Chris Wilson wrote: Use the new idr_init_base() function to create an IDR that knows id==0 is never allocated as it maps to an invalid identifier. By knowing that id==0 is invalid, the IDR can start from

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Report setup errors for igt_partial_tiling

== Series Details == Series: drm/i915/selftests: Report setup errors for igt_partial_tiling URL : https://patchwork.freedesktop.org/series/38154/ State : success == Summary == Series 38154v1 drm/i915/selftests: Report setup errors for igt_partial_tiling

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tuesday 13 February 2018 15:27:26 Ville Syrjälä wrote: > On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote: > > On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote: > > > Hi! I'm periodically getting following message in dmesg on Lenovo > > > Thinkpad X1 Carbon 3rd generation: > > >

Re: [Intel-gfx] [PATCH] drm/i915: Release the atomic kmap relocation cache around snb GTT w/a

On 13/02/2018 13:46, Chris Wilson wrote: Quoting Chris Wilson (2018-02-13 13:45:33) Quoting Tvrtko Ursulin (2018-02-13 13:42:03) On 12/02/2018 21:11, Chris Wilson wrote: When we need to rebind the vma into the global GTT for snb, we need to drop the current reloc_cache as it will be holding

[Intel-gfx] [PATCH 1/4] drm/i915: Lock out execlist tasklet while peeking inside for busy-stats

From: Chris Wilson In order to prevent a race condition where we may end up overaccounting the active state and leaving the busy-stats believing the GPU is 100% busy, lock out the tasklet while we reconstruct the busy state. There is no direct spinlock guard for the

[Intel-gfx] [PATCH 3/4] drm/i915/pmu: Fix sleep under atomic in RC6 readout

From: Tvrtko Ursulin We are not allowed to call intel_runtime_pm_get from the PMU counter read callback since the former can sleep, and the latter is running under IRQ context. To workaround this, we record the last known RC6 and while runtime suspended estimate its

[Intel-gfx] [PATCH 2/4] drm/i915/pmu: Fix PMU enable vs execlists tasklet race

From: Tvrtko Ursulin Commit 99e48bf98dd0 ("drm/i915: Lock out execlist tasklet while peeking inside for busy-stats") added a tasklet_disable call in busy stats enabling, but we failed to understand that the PMU enable callback runs as an hard IRQ (IPI). Consequence of

[Intel-gfx] [PATCH 4/4] drm/i915/pmu: Fix building without CONFIG_PM

From: Chris Wilson As we peek inside struct device to query members guarded by CONFIG_PM, so must be the code. Reported-by: kbuild test robot Fixes: 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout") Signed-off-by: Chris

[Intel-gfx] [PATCH] drm/i915/selftests: Report setup errors for igt_partial_tiling

igt_partial_tiling managed to fail with an -EBUSY. This usually means a pin leak, but that should be impossible given the test setup. Add a couple of error messages to help identify the path that failed. References: https://bugs.freedesktop.org/show_bug.cgi?id=105073 Signed-off-by: Chris Wilson

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Prepare for more rings

== Series Details == Series: drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/38150/ State : success == Summary == Series 38150v1 drm/i915/icl: Prepare for more rings https://patchwork.freedesktop.org/api/1.0/series/38150/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report setup errors for igt_partial_tiling

Chris Wilson writes: > igt_partial_tiling managed to fail with an -EBUSY. This usually means a > pin leak, but that should be impossible given the test setup. Add a > couple of error messages to help identify the path that failed. > > References:

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote: > On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote: > > Hi! I'm periodically getting following message in dmesg on Lenovo > > Thinkpad X1 Carbon 3rd generation: > > > > [drm] Reducing the compressed framebuffer size. This may lead

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote: From: Abhijeet Kumar Finite loop and msleep was causing few igt@pm_rpm tests failure for HSW and BDW. Thus removing them. Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to sync

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Report setup errors for igt_partial_tiling

Quoting Mika Kuoppala (2018-02-13 12:17:51) > Chris Wilson writes: > > > igt_partial_tiling managed to fail with an -EBUSY. This usually means a > > pin leak, but that should be impossible given the test setup. Add a > > couple of error messages to help identify the

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On Tue, 13 Feb 2018 13:47:25 +0100, Chris Wilson wrote: > > Quoting Kumar, Abhijeet (2018-02-13 12:41:42) > > > > > > On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote: > > > > From: Abhijeet Kumar > > > > Finite loop and msleep was causing few igt@pm_rpm

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On 2/13/2018 6:17 PM, Chris Wilson wrote: Quoting Kumar, Abhijeet (2018-02-13 12:41:42) On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote: From: Abhijeet Kumar Finite loop and msleep was causing few igt@pm_rpm tests failure for HSW and BDW. Thus

[Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2)

== Series Details == Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2) URL : https://patchwork.freedesktop.org/series/38140/ State : success == Summary == Series 38140v2 ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

Re: [Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

Quoting Kumar, Abhijeet (2018-02-13 12:41:42) > > > On 2/13/2018 3:54 PM, abhijeet.ku...@intel.com wrote: > > From: Abhijeet Kumar > > Finite loop and msleep was causing few igt@pm_rpm tests failure > for HSW and BDW. Thus removing them. > > Fixes:

Re: [Intel-gfx] [PATCH] drm/i915: Release the atomic kmap relocation cache around snb GTT w/a

Quoting Chris Wilson (2018-02-13 13:45:33) > Quoting Tvrtko Ursulin (2018-02-13 13:42:03) > > > > On 12/02/2018 21:11, Chris Wilson wrote: > > > When we need to rebind the vma into the global GTT for snb, we need to > > > drop the current reloc_cache as it will be holding a kmap_atomic() and > >

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

Quoting Takashi Iwai (2018-02-13 08:30:52) > On Tue, 13 Feb 2018 09:26:32 +0100, > Saarinen, Jani wrote: > > > > Hi, > > > -Original Message- > > > From: Takashi Iwai [mailto:ti...@suse.de] > > > Sent: tiistai 13. helmikuuta 2018 10.14 > > > To: Saarinen, Jani >

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

Quoting Patchwork (2018-02-13 09:42:41) > == Series Details == > > Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() > URL : https://patchwork.freedesktop.org/series/38140/ > State : success > > == Summary == > > Series 38140v1 ALSA: hda: Remove finite loop from

[Intel-gfx] ✗ Fi.CI.BAT: failure for Adding NV12 support (rev9)

== Series Details == Series: Adding NV12 support (rev9) URL : https://patchwork.freedesktop.org/series/28103/ State : failure == Summary == Series 28103v9 Adding NV12 support https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/9/mbox/ Test debugfs_test: Subgroup

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

On 2/13/2018 1:44 PM, Takashi Iwai wrote: On Tue, 13 Feb 2018 08:34:40 +0100, Saarinen, Jani wrote: HI, -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Takashi Iwai Sent: tiistai 13. helmikuuta 2018 7.11 To: Chris Wilson

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

Hi, > -Original Message- > From: Takashi Iwai [mailto:ti...@suse.de] > Sent: tiistai 13. helmikuuta 2018 10.14 > To: Saarinen, Jani > Cc: Chris Wilson ; intel-gfx@lists.freedesktop.org; > Kumar, Abhijeet >

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Mon, Feb 12, 2018 at 01:58:32PM -0500, Alex Deucher wrote: > On Mon, Feb 12, 2018 at 4:45 AM, Lukas Wunner wrote: > > On Mon, Feb 12, 2018 at 09:03:26AM +, Mike Lothian wrote: > >> On 12 February 2018 at 03:39, Lukas Wunner wrote: > >> > On Mon, Feb 12,

[Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

== Series Details == Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() URL : https://patchwork.freedesktop.org/series/38140/ State : success == Summary == Series 38140v1 ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

[Intel-gfx] [PATCH 00/16] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated

Re: [Intel-gfx] [PATCH 0/5] drm/i915: Grab the vblank evasion lock around the entire evasion.

Quoting Maarten Lankhorst (2018-02-13 10:19:42) > Op 12-02-18 om 18:01 schreef Ville Syrjälä: > > On Fri, Feb 09, 2018 at 06:21:08PM +0100, Maarten Lankhorst wrote: > >> Op 09-02-18 om 11:04 schreef Chris Wilson: > >>> Quoting Maarten Lankhorst (2018-02-09 09:53:59) > Some cleanups to move

[Intel-gfx] [PATCH v2] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

From: Abhijeet Kumar Finite loop and msleep was causing few igt@pm_rpm tests failure for HSW and BDW. Thus removing them. Fixes: 3b5b899ca67d ("ALSA: hda: Make use of core codec functions to sync power state") References:

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

Hi Lukas, On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > Fix a deadlock on hybrid graphics laptops that's been present since 2013: > > DRM drivers poll connectors in 10 sec intervals. The poll worker is > stopped on ->runtime_suspend with cancel_delayed_work_sync(). However >

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

On Tue, 13 Feb 2018 08:34:40 +0100, Saarinen, Jani wrote: > > HI, > > -Original Message- > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf > > Of > > Takashi Iwai > > Sent: tiistai 13. helmikuuta 2018 7.11 > > To: Chris Wilson > >

[Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Trim max number of contexts used

icl offers a much reduced context space, and in its simplest setup we cannot allocate one context per priority level, so trim the number and reuse the same context for multiple priority requests. Signed-off-by: Chris Wilson --- tests/gem_exec_schedule.c | 38

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On 2/13/2018 3:15 PM, Chris Wilson wrote: Quoting Patchwork (2018-02-13 09:42:41) == Series Details == Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() URL : https://patchwork.freedesktop.org/series/38140/ State : success == Summary == Series 38140v1 ALSA: hda:

Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited Range Color Handling

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Friday, February 9, 2018 9:09 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ; >Syrjala, Ville ;

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

On 2/13/2018 2:00 PM, Takashi Iwai wrote: On Tue, 13 Feb 2018 09:26:32 +0100, Saarinen, Jani wrote: Hi, -Original Message- From: Takashi Iwai [mailto:ti...@suse.de] Sent: tiistai 13. helmikuuta 2018 10.14 To: Saarinen, Jani Cc: Chris Wilson

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Keep vblank irq enabled during vblank evasion.

Op 12-02-18 om 21:55 schreef Chris Wilson: > Quoting Ville Syrjälä (2018-02-12 18:06:58) >> On Mon, Feb 12, 2018 at 05:24:54PM +, Chris Wilson wrote: >>> Quoting Ville Syrjälä (2018-02-12 16:55:28) On Mon, Feb 12, 2018 at 04:41:05PM +0100, Maarten Lankhorst wrote: > Op 12-02-18 om

Re: [Intel-gfx] [PATCH] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

On Tue, 13 Feb 2018 10:09:48 +0100, abhijeet.ku...@intel.com wrote: > > From: Abhijeet Kumar > > Finite loop was causing few igt@pm_rpm tests failure for HSW and BDW. > Thus changing it back to infinite one. This missing the explanation why the finite loop fails. I

Re: [Intel-gfx] patches that failed to cherry-pick on drm-intel-fixes for 4.16-rc1

On 13/02/18 07:38, Rodrigo Vivi wrote: These patches failed to cherry-pick on drm-intel-fixes Please provide a backport or advise how to proceed. fd10e2ce9905 ("drm/i915/breadcrumbs: Ignore unsubmitted signalers") 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout") I'm

[Intel-gfx] [PATCH 4/4] drm/i915/pmu: Fix building without CONFIG_PM

From: Chris Wilson As we peek inside struct device to query members guarded by CONFIG_PM, so must be the code. Reported-by: kbuild test robot Fixes: 1fe699e30113 ("drm/i915/pmu: Fix sleep under atomic in RC6 readout") Signed-off-by: Chris

[Intel-gfx] [PATCH 2/4] drm/i915/pmu: Fix PMU enable vs execlists tasklet race

From: Tvrtko Ursulin Commit 99e48bf98dd0 ("drm/i915: Lock out execlist tasklet while peeking inside for busy-stats") added a tasklet_disable call in busy stats enabling, but we failed to understand that the PMU enable callback runs as an hard IRQ (IPI). Consequence of

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/breadcrumbs: Ignore unsubmitted signalers (rev2)

== Series Details == Series: drm/i915/breadcrumbs: Ignore unsubmitted signalers (rev2) URL : https://patchwork.freedesktop.org/series/37724/ State : failure == Summary == Applying: drm/i915/breadcrumbs: Ignore unsubmitted signalers error: Failed to merge in the changes. Using index info to

Re: [Intel-gfx] [PATCH 0/5] drm/i915: Grab the vblank evasion lock around the entire evasion.

Op 12-02-18 om 18:01 schreef Ville Syrjälä: > On Fri, Feb 09, 2018 at 06:21:08PM +0100, Maarten Lankhorst wrote: >> Op 09-02-18 om 11:04 schreef Chris Wilson: >>> Quoting Maarten Lankhorst (2018-02-09 09:53:59) Some cleanups to move the uncore.lock around vblank evasion, so run to

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

Thanks for sharing the results Marta and Jani. I'll fix it and send the updated patch soon. Warm Regards, Abhijeet ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

Hi, On 2/7/2018 10:12 PM, Sharma, Shashank wrote: Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by:

Re: [Intel-gfx] [PATCH] AWOOGA: Revert "ALSA: hda: Make use of core codec functions to sync power state"

On Tue, 13 Feb 2018 09:26:32 +0100, Saarinen, Jani wrote: > > Hi, > > -Original Message- > > From: Takashi Iwai [mailto:ti...@suse.de] > > Sent: tiistai 13. helmikuuta 2018 10.14 > > To: Saarinen, Jani > > Cc: Chris Wilson ; > >

[Intel-gfx] [PATCH 1/4] drm/i915: Lock out execlist tasklet while peeking inside for busy-stats

From: Chris Wilson In order to prevent a race condition where we may end up overaccounting the active state and leaving the busy-stats believing the GPU is 100% busy, lock out the tasklet while we reconstruct the busy state. There is no direct spinlock guard for the

[Intel-gfx] [PATCH 3/4] drm/i915/pmu: Fix sleep under atomic in RC6 readout

From: Tvrtko Ursulin We are not allowed to call intel_runtime_pm_get from the PMU counter read callback since the former can sleep, and the latter is running under IRQ context. To workaround this, we record the last known RC6 and while runtime suspended estimate its

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1:

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. Signed-off-by: Mahesh Kumar ---

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

From: Chandra Konduru This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

From: Chandra Konduru This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote: > Hi! I'm periodically getting following message in dmesg on Lenovo > Thinkpad X1 Carbon 3rd generation: > > [drm] Reducing the compressed framebuffer size. This may lead to less power > savings than a non-reduced-size. Try to increase

[Intel-gfx] [PATCH] ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

From: Abhijeet Kumar Finite loop was causing few igt@pm_rpm tests failure for HSW and BDW. Thus changing it back to infinite one. References: https://bugs.freedesktop.org/show_bug.cgi?id=105069 Signed-off-by: Abhijeet Kumar ---

Re: [Intel-gfx] patches that failed to cherry-pick on drm-intel-fixes for 4.16-rc1

On Tue, 13 Feb 2018, Tvrtko Ursulin wrote: > On 13/02/18 07:38, Rodrigo Vivi wrote: >> >> These patches failed to cherry-pick on drm-intel-fixes >> >> Please provide a backport or advise how to proceed. >> >> fd10e2ce9905 ("drm/i915/breadcrumbs: Ignore unsubmitted

[Intel-gfx] [PATCH] drm/i915/breadcrumbs: Ignore unsubmitted signalers

When a request is preempted, it is unsubmitted from the HW queue and removed from the active list of breadcrumbs. In the process, this however triggers the signaler and it may see the clear rbtree with the old, and still valid, seqno, or it may match the cleared seqno with the now zero

Re: [Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

On Tue, 2018-02-13 at 15:22 +0530, Vidya Srinivas wrote: > From: Mahesh Kumar > > Add support of recognizing DRM_FORMAT_NV12 from plane_format > register value. > Reviewed-by: Mika Kahola > Signed-off-by: Mahesh Kumar

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state()

Hi, Still fails. > -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Patchwork > Sent: tiistai 13. helmikuuta 2018 11.43 > To: Kumar, Abhijeet > Cc: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] ✓

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Prepare for more rings

== Series Details == Series: drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/38150/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-shrfb-draw-pwrite: fail -> PASS (shard-apl)

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Report setup errors for igt_partial_tiling

== Series Details == Series: drm/i915/selftests: Report setup errors for igt_partial_tiling URL : https://patchwork.freedesktop.org/series/38154/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Subgroup

Re: [Intel-gfx] [PATCH v5] drm/i915: Handle RC6 counter wrap

On Tue, Feb 13, 2018 at 02:09:51PM +, Tvrtko Ursulin wrote: > > On 08/02/2018 16:04, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-02-08 16:00:36) > >> From: Tvrtko Ursulin > >> > >> We can implement limited RC6 counter wrap-around protection under the > >>

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Enable VBT based BL control for DP (v2)

On Fri, 09 Feb 2018, "Mustaffa, Mustamin B" wrote: > May I know why the need to use connector as connector wasn't > initialized in parent function ' intel_pps_get_registers'? Oh, right, I overlooked that. > While ' dev_priv' already initialized which also already

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915/guc: Add HuC firmware size related restriction for Gen9 and CNL A0

On Tue, 13 Feb 2018 00:45:51 +0100, Jackie Li wrote: On CNL A0 and Gen9, there's a hardware restriction that requires the available GuC WOPCM size to be larger than or equal to HuC firmware size. This patch adds new verfication code to ensure the available GuC WOPCM

[Intel-gfx] [PATCH] drm/i915: Fix i915_gem_context.h header

From: Tvrtko Ursulin Header uses I915_NUM_ENGINES so needs to include i915.gem.h, and also it uses requests so we can forward declare struct drm_i915_gem_request. Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson

Re: [Intel-gfx] [PATCH 1/4] drm/i915: abstract PCH type detection from PCH id

On Mon, 05 Feb 2018, Rodrigo Vivi wrote: > On Mon, Feb 05, 2018 at 05:31:36PM +, Jani Nikula wrote: >> Make the logic in intel_detect_pch() easier to follow, and make the PCH >> id to type mapping reusable. No functional changes. > > I wondered here if we should change

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tuesday 13 February 2018 17:36:54 Ville Syrjälä wrote: > On Tue, Feb 13, 2018 at 02:38:42PM +0100, Pali Rohár wrote: > > On Tuesday 13 February 2018 15:27:26 Ville Syrjälä wrote: > > > On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote: > > > > On Tuesday 06 February 2018 16:21:43 Pali

Re: [Intel-gfx] [PATCH stable-4.14 0/3] drm/i915: Fix plane regression

On Thu, Feb 01, 2018 at 06:48:30PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > These backports fix a plane related regression causing a corrupted > screen and bunch of WARNs from the kernel on some pre-i965 era > hardware. > > Cc:

Re: [Intel-gfx] [igt-dev] [PATCH igt] igt/perf_pmu: Skip hotplugging cpu0

On 13/02/2018 16:05, Chris Wilson wrote: It is a known issue that some "commodity" machines fail when asked to hotplug CPU0, so don't. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin -- Tvrtko, is it just this simple? Or do we need to avoid

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Tue, Feb 13, 2018 at 12:52:06PM +0100, Lukas Wunner wrote: > On Tue, Feb 13, 2018 at 10:55:06AM +, Liviu Dudau wrote: > > On Sun, Feb 11, 2018 at 10:38:28AM +0100, Lukas Wunner wrote: > > > DRM drivers poll connectors in 10 sec intervals. The poll worker is > > > stopped on

Re: [Intel-gfx] [PATCH 1/4] drm/i915: abstract PCH type detection from PCH id

On Tue, Feb 13, 2018 at 05:35:58PM +0200, Jani Nikula wrote: > On Mon, 05 Feb 2018, Rodrigo Vivi wrote: > > On Mon, Feb 05, 2018 at 05:31:36PM +, Jani Nikula wrote: > >> Make the logic in intel_detect_pch() easier to follow, and make the PCH > >> id to type mapping

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix i915_gem_context.h header

On 13/02/2018 14:47, Patchwork wrote: == Series Details == Series: drm/i915: Fix i915_gem_context.h header URL : https://patchwork.freedesktop.org/series/38164/ State : success == Summary == Series 38164v1 drm/i915: Fix i915_gem_context.h header

Re: [Intel-gfx] [PATCH v5] drm/i915: Handle RC6 counter wrap

On 08/02/2018 16:04, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-08 16:00:36) From: Tvrtko Ursulin We can implement limited RC6 counter wrap-around protection under the assumption that clients will be reading this value more frequently than the wrap period

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix i915_gem_context.h header

== Series Details == Series: drm/i915: Fix i915_gem_context.h header URL : https://patchwork.freedesktop.org/series/38164/ State : success == Summary == Series 38164v1 drm/i915: Fix i915_gem_context.h header https://patchwork.freedesktop.org/api/1.0/series/38164/revisions/1/mbox/ Test

[Intel-gfx] ✗ Fi.CI.IGT: warning for ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2)

== Series Details == Series: ALSA: hda: Remove finite loop from snd_hdac_sync_power_state() (rev2) URL : https://patchwork.freedesktop.org/series/38140/ State : warning == Summary == Test kms_vblank: Subgroup pipe-a-wait-forked: pass -> SKIP (shard-snb)

Re: [Intel-gfx] [PATCH] drm/i915: Fix i915_gem_context.h header

Quoting Tvrtko Ursulin (2018-02-13 14:18:33) > From: Tvrtko Ursulin > > Header uses I915_NUM_ENGINES so needs to include i915.gem.h, and also > it uses requests so we can forward declare struct drm_i915_gem_request. > > Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH 0/5] Fix deadlock on runtime suspend in DRM drivers

On Tue, Feb 13, 2018 at 3:17 AM, Lukas Wunner wrote: > On Mon, Feb 12, 2018 at 01:58:32PM -0500, Alex Deucher wrote: >> On Mon, Feb 12, 2018 at 4:45 AM, Lukas Wunner wrote: >> > On Mon, Feb 12, 2018 at 09:03:26AM +, Mike Lothian wrote: >> >> On 12 February

Re: [Intel-gfx] [PATCH v10 3/7] drm/i915/guc: Implement dynamic GuC WOPCM offset and size

On Tue, 13 Feb 2018 00:45:49 +0100, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM offset and size. On Gen9, the value of the GuC WOPCM size register needs to be larger than the value of GuC WOPCM offset register + a Gen9 specific offset (144KB)

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tue, Feb 13, 2018 at 05:04:37PM +0100, Pali Rohár wrote: > On Tuesday 13 February 2018 17:36:54 Ville Syrjälä wrote: > > On Tue, Feb 13, 2018 at 02:38:42PM +0100, Pali Rohár wrote: > > > On Tuesday 13 February 2018 15:27:26 Ville Syrjälä wrote: > > > > On Tue, Feb 13, 2018 at 09:50:30AM +0100,

Re: [Intel-gfx] Thinkpad X1 Carbon 3rd - Reducing the compressed framebuffer size

On Tue, Feb 13, 2018 at 02:38:42PM +0100, Pali Rohár wrote: > On Tuesday 13 February 2018 15:27:26 Ville Syrjälä wrote: > > On Tue, Feb 13, 2018 at 09:50:30AM +0100, Pali Rohár wrote: > > > On Tuesday 06 February 2018 16:21:43 Pali Rohár wrote: > > > > Hi! I'm periodically getting following

Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited Range Color Handling

On Tue, Feb 13, 2018 at 10:37:03AM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, February 9, 2018 9:09 PM > >To: Shankar, Uma > >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson

[Intel-gfx] [PATCH igt] igt/perf_pmu: Skip hotplugging cpu0

It is a known issue that some "commodity" machines fail when asked to hotplug CPU0, so don't. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin -- Tvrtko, is it just this simple? Or do we need to avoid the physical package? -Chris ---

  1   2   3   >