On 24/02/2018 19:14, Chris Wilson wrote:
Although we want to specify exactly which physical engine to run on, the
busy ioctl can only return the I915_EXEC_RING identifier, i.e. the
aliased I915_EXEC_BSD for vcs0/vcs1. Horrors.
Signed-off-by: Chris Wilson
---
tests/gem_busy.c | 7 ---
1
On Thu, 22 Feb 2018, Daniel Thompson wrote:
> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>> were adapted to this change.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> arch/arm/mach-s3c24xx/mach-rx
On Fri, Feb 23, 2018 at 02:20:59PM +, Tvrtko Ursulin wrote:
>
> On 23/02/2018 11:58, Petri Latvala wrote:
> > We have IGT_HANG and IGT_HANG_WITHOUT_RESET so the users can opt
> > in/out of some fatal behaviour already. I'm fine with auto-rebooting,
> > even as the default, if users can opt out
On 02/26/2018 12:03 PM, Petri Latvala wrote:
On Fri, Feb 23, 2018 at 02:20:59PM +, Tvrtko Ursulin wrote:
On 23/02/2018 11:58, Petri Latvala wrote:
We have IGT_HANG and IGT_HANG_WITHOUT_RESET so the users can opt
in/out of some fatal behaviour already. I'm fine with auto-rebooting,
even as
On Fri, 23 Feb 2018, Oscar Mateo wrote:
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> new file mode 100644
> index 000..bd23418
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -0,0 +1,684 @@
> +/*
> + * SPDX-Licens
I'll rebase it on latest for-next in next version.
Thank you,
Claudiu Beznea
On 24.02.2018 22:49, kbuild test robot wrote:
> Hi Claudiu,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on pwm/for-next]
> [also build test WARNING on v4.16-rc2 next-20180223
On Tue, 20 Feb 2018, Chris Wilson wrote:
> We make use of unsafe kernel parameters in igt, which generates a
> warning and taints the kernel. The warning is unhelpful as we then need
> to filter it out again, so kill it at source.
Is your goal to upstream this or what?
BR,
Jani.
>
> Cc: Petri L
When searching for a VGA connector to use to test overriding the
connector status, we require the system to have a disconnected VGA
connector, but if a previous test left an override inplace, that may not
exist. Before we check whether the connector is attached to real HW,
first reset the connector
Quoting Jani Nikula (2018-02-26 10:42:40)
> On Tue, 20 Feb 2018, Chris Wilson wrote:
> > We make use of unsafe kernel parameters in igt, which generates a
> > warning and taints the kernel. The warning is unhelpful as we then need
> > to filter it out again, so kill it at source.
>
> Is your goal
the system]
url:
https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/Enabling-VDSC-in-i915-driver-for-GLK/20180226-114246
coccinelle warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/intel_vdsc.c:828:2-3: Unneeded semicolon
vim +828 drivers/gpu/drm/i915/intel_vd
On Mon, 26 Feb 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-02-26 10:42:40)
>> On Tue, 20 Feb 2018, Chris Wilson wrote:
>> > We make use of unsafe kernel parameters in igt, which generates a
>> > warning and taints the kernel. The warning is unhelpful as we then need
>> > to filter it ou
Reviewed-by: Marta Lofstedt
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, February 26, 2018 12:44 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: igt-...@lists.freedesktop.org; Chris Wilson ;
> Lofstedt, Marta
> Subject: [PATCH igt] igt/kms_fo
Op 26-02-18 om 11:43 schreef Chris Wilson:
> When searching for a VGA connector to use to test overriding the
> connector status, we require the system to have a disconnected VGA
> connector, but if a previous test left an override inplace, that may not
> exist. Before we check whether the connecto
On Mon, 26 Feb 2018 07:58:49 +0100, Sagar Arun Kamble
wrote:
On 2/23/2018 7:40 PM, Michal Wajdeczko wrote:
We want to use higher level 'uc' functions as the main entry points to
the GuC/HuC code to hide some details and keep code layered.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Ka
For large oops dump, for example if ftrace is included, we can easily
exceed the storage buffer and lose the most important bit of
information: where the OOPS occurred. So repeat the location information
just before the end marker.
Signed-off-by: Chris Wilson
Cc: Marta Lofstedt
---
kernel/panic
Seems like a good idea to me.
+Mika
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, February 26, 2018 3:53 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Lofstedt, Marta
>
> Subject: [RFC] kernel/panic: Repeat the line and caller
On Thu, 22 Feb 2018, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Introduce subplatform mask to eliminate throughout the code devid checking
> sprinkle, mostly courtesy of IS_*_UL[TX] macros.
>
> Subplatform mask initialization is moved either to static tables (Ironlake
> M) or runtime device
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_p
Since we're inhibiting context save of preempt context, we're no longer
tracking the position of HEAD/TAIL. With GuC, we're adding a new
breadcrumb for each preemption, which means that the HW will do more and
more breadcrumb writes. Eventually the ring is filled, and we're
submitting the preemptio
== Series Details ==
Series: kernel/panic: Repeat the line and caller information at the end of the
OOPS
URL : https://patchwork.freedesktop.org/series/38962/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include
On 26.02.2018 11:57, Jani Nikula wrote:
> On Thu, 22 Feb 2018, Daniel Thompson wrote:
>> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>>> were adapted to this change.
>>>
>>> Signed-off-by: Claudiu
Quoting Michał Winiarski (2018-02-26 13:59:59)
> Since we're inhibiting context save of preempt context, we're no longer
> tracking the position of HEAD/TAIL. With GuC, we're adding a new
> breadcrumb for each preemption, which means that the HW will do more and
> more breadcrumb writes. Eventually
For large oops dump, for example if ftrace is included, we can easily
exceed the storage buffer and lose the most important bit of
information: where the OOPS occurred. So repeat the location information
just before the end marker.
Signed-off-by: Chris Wilson
Cc: Marta Lofstedt
---
git add ftw
-
Quoting Chris Wilson (2018-02-26 14:28:36)
> Quoting Michał Winiarski (2018-02-26 13:59:59)
> > + for_each_engine(engine, dev_priv, id) {
> struct intel_engine *ce = &client->owner->engine[id];
>
> /* The preempt context must be pinned on each engine);
>
Quoting Chris Wilson (2018-02-26 14:28:36)
> Quoting Michał Winiarski (2018-02-26 13:59:59)
> > + for_each_engine(engine, dev_priv, id) {
> struct intel_engine *ce = &client->owner->engine[id];
>
> /* The preempt context must be pinned on each engine);
>
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Fill preempt context once at
init time
URL : https://patchwork.freedesktop.org/series/38964/
State : success
== Summary ==
Series 38964v1 series starting with [1/2] drm/i915/guc: Fill preempt context
once at init time
http
On Sun, Feb 25, 2018 at 12:42:30AM +0100, Lukas Wunner wrote:
> DRM drivers need to tell vga_switcheroo whether they use runtime PM.
> If they do use it, vga_switcheroo lets them autosuspend at their own
> discretion. If on the other hand they do not use it, vga_switcheroo
> allows the user to sus
On Wed, Jan 10, 2018 at 02:04:57PM +0100, Daniel Vetter wrote:
> On Fri, Dec 22, 2017 at 09:22:30PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we only check that the plane supports the pixel format of the
> > fb we're about to feed to it. Extend it to check also the mod
Quoting Chris Wilson (2018-02-26 14:38:20)
> Quoting Chris Wilson (2018-02-26 14:28:36)
> > Quoting Michał Winiarski (2018-02-26 13:59:59)
> > > + for_each_engine(engine, dev_priv, id) {
> > struct intel_engine *ce = &client->owner->engine[id];
> >
> > /* The
Quoting Chris Wilson (2018-02-26 14:28:36)
> Quoting Michał Winiarski (2018-02-26 13:59:59)
> > + if (id == RCS) {
> > + cs = gen8_emit_ggtt_write_rcs(cs,
> > GUC_PREEMPT_FINISHED,
> > +
> > intel_hws_preempt_done_address(e
== Series Details ==
Series: kernel/panic: Repeat the line and caller information at the end of the
OOPS (rev2)
URL : https://patchwork.freedesktop.org/series/38962/
State : success
== Summary ==
Series 38962v2 kernel/panic: Repeat the line and caller information at the end
of the OOPS
https
Quoting Chris Wilson (2018-02-26 14:28:36)
> Quoting Michał Winiarski (2018-02-26 13:59:59)
> > + for_each_engine(engine, dev_priv, id) {
> struct intel_engine *ce = &client->owner->engine[id];
>
> /* The preempt context must be pinned on each engine);
>
As using an unsafe module parameter is, by its very definition, an
expected user action, emitting a warning is overkill. Nothing has yet
gone wrong, and we add a taint flag for any future oops should
something actually go wrong. So instead of having a user controllable
pr_warn, downgrade it to a pr
In investigating the issue with having to force preemption within the
executing ELSP[], we want to trigger preemption between all elements of
that array. To that end, we issue a series of requests with different
priorities to fill the in-flight ELSP[] and then demand preemption into
the middle of t
On Mon, 26 Feb 2018, Chris Wilson wrote:
> As using an unsafe module parameter is, by its very definition, an
> expected user action, emitting a warning is overkill. Nothing has yet
> gone wrong, and we add a taint flag for any future oops should
> something actually go wrong. So instead of having
== Series Details ==
Series: kernel: Downgrade warning for unsafe parameters (rev2)
URL : https://patchwork.freedesktop.org/series/38614/
State : success
== Summary ==
Series 38614v2 kernel: Downgrade warning for unsafe parameters
https://patchwork.freedesktop.org/api/1.0/series/38614/revision
Quoting Jani Nikula (2018-02-26 14:00:37)
> On Thu, 22 Feb 2018, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Introduce subplatform mask to eliminate throughout the code devid checking
> > sprinkle, mostly courtesy of IS_*_UL[TX] macros.
> >
> > Subplatform mask initialization is moved
On Mon, Feb 26, 2018 at 04:41:09PM +0200, Imre Deak wrote:
> On Sun, Feb 25, 2018 at 12:42:30AM +0100, Lukas Wunner wrote:
> > DRM drivers need to tell vga_switcheroo whether they use runtime PM.
> > If they do use it, vga_switcheroo lets them autosuspend at their own
> > discretion. If on the oth
On Mon, 26 Feb 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-02-26 14:00:37)
>> On Thu, 22 Feb 2018, Tvrtko Ursulin wrote:
>> > From: Tvrtko Ursulin
>> >
>> > Introduce subplatform mask to eliminate throughout the code devid checking
>> > sprinkle, mostly courtesy of IS_*_UL[TX] macros.
Since we're inhibiting context save of preempt context, we're no longer
tracking the position of HEAD/TAIL. With GuC, we're adding a new
breadcrumb for each preemption, which means that the HW will do more and
more breadcrumb writes. Eventually the ring is filled, and we're
submitting the preemptio
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_p
On 25/02/18 22:17, Sagar Arun Kamble wrote:
On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix
HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.
This patch enables the hdcp initialization for HSW, BDW, and BXT.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 31 ++
This series addresses the requriement of below HDCP compliance tests
DP: 1A-06 and 1B-05
HDMI: 1A-04 and 1A-07a
One of the patch uses the I915 power infra-structure for checking
the power state of PW#1. Which enables the init path for all legacy
platforms.
And encoder specific msg
In case of V prime mismatch, DP HDCP spec mandates the re-read of
Vprime atleast twice.
DP HDCP CTS Test: 1B-05
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/dr
As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.
And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.
DP CT
In a connected state, If a HDMI HDCP sink is responded with NACK for
HDCP I2C register access, then HDMI HDCP spec mandates the polling
of any HDCP space registers for accessibility, minimum once in 2Secs
atleast for 4Secs.
Just to make it simple, this is generically implemented for both HDMI
and
DP and HDMI HDCP specifications are varying with respect to
detecting the R0 and ksv_fifo availability.
DP will produce CP_IRQ and set a bit for indicating the R0 and
FIFO_READY status.
Whereas HDMI will set a bit for FIFO_READY but there is no bit
indication for R0 ready. And also polling of REA
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Fill preempt context once
at init time
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Series 38975v1 series starting with [v2,1/2] drm/i915/guc: Fill preempt context
once at init tim
On Mon, Feb 26, 2018 at 10:42:35PM +0530, Ramalingam C wrote:
> As per DP spec when R0 mismatch is detected, HDCP source supported
> re-read the R0 atleast twice.
>
> And For HDMI and DP minimum wait required for the R0 availability is
> 100mSec. So this patch changes the wait time to 100mSec but
On Mon, Feb 26, 2018 at 10:42:36PM +0530, Ramalingam C wrote:
> In case of V prime mismatch, DP HDCP spec mandates the re-read of
> Vprime atleast twice.
>
> DP HDCP CTS Test: 1B-05
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 10 +-
> 1 file changed, 9 in
== Series Details ==
Series: HDCP1.4 fixes
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Series 38978v1 HDCP1.4 fixes
https://patchwork.freedesktop.org/api/1.0/series/38978/revisions/1/mbox/
Known issues:
Test debugfs_test:
Subgroup read_all
On Mon, Feb 26, 2018 at 10:42:37PM +0530, Ramalingam C wrote:
> HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
> is enabled. Using the I915 power well infrastruture, above requirement
> is verified.
>
> This patch enables the hdcp initialization for HSW, BDW, and BXT.
>
>
On Mon, Feb 26, 2018 at 10:42:38PM +0530, Ramalingam C wrote:
> In a connected state, If a HDMI HDCP sink is responded with NACK for
> HDCP I2C register access, then HDMI HDCP spec mandates the polling
> of any HDCP space registers for accessibility, minimum once in 2Secs
> atleast for 4Secs.
>
I
While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.
slice0: 3 subslice(s) (0x7):
subslice0: 8 EUs (0xff)
subslice1: 8 EUs (0xff)
subslice2: 8 EUs (0xff
This might be useful information for developers looking at an error
state.
v2: Place topology towards the end of the error state (Chris)
v3: Reuse common printing code (Michal)
v4: Make this a one-liner (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
Acked-by: Chris Wilso
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slic
Now that we have that information in topology fields, let's just reuse it.
v2: Style tweaks (Tvrtko)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 27 +++
drivers/gpu/drm/i915/intel_de
With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.
This is essential for monitoring parts o
Hi all,
Here is another update to fix a couple of bugs in the first patch :
- HSW was reporting the eu masks incorrectly
- debugfs was reporting incorrect subslice numbers (and failing
igt@pm_sseu), the igt has been update to handle kernels before and
after this series.
Cheers,
Lionel
There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die
On Mon, Feb 26, 2018 at 10:42:39PM +0530, Ramalingam C wrote:
> DP and HDMI HDCP specifications are varying with respect to
> detecting the R0 and ksv_fifo availability.
>
> DP will produce CP_IRQ and set a bit for indicating the R0 and
> FIFO_READY status.
I'm not sure what the benefit is? Keepi
== Series Details ==
Series: drm/i915: expose RCS topology to userspace
URL : https://patchwork.freedesktop.org/series/38981/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Fill preempt context once at
init time
URL : https://patchwork.freedesktop.org/series/38964/
State : success
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
== Series Details ==
Series: kernel/panic: Repeat the line and caller information at the end of the
OOPS (rev2)
URL : https://patchwork.freedesktop.org/series/38962/
State : success
== Summary ==
Possible new issues:
Test pm_rc6_residency:
Subgroup rc6-accuracy:
Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slic
On Fri, 2018-02-23 at 19:12 -0800, Pandiyan, Dhinakaran wrote:
> On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent access
On Fri, Feb 23, 2018 at 05:51:40PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separ
From: Michał Winiarski
Since we're inhibiting context save of preempt context, we're no longer
tracking the position of HEAD/TAIL. With GuC, we're adding a new
breadcrumb for each preemption, which means that the HW will do more and
more breadcrumb writes. Eventually the ring is filled, and we're
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: store all subslice masks
Okay!
Commit: drm/i915/debugfs: reuse max slice/subslices a
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : success
== Summary ==
Series 38981v2 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/38981/revisions/2/mbox/
== Series Details ==
Series: series starting with drm/i915/guc: Fill preempt context once at init
time (rev2)
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Series 38975v2 series starting with drm/i915/guc: Fill preempt context once at
init time
https://p
== Series Details ==
Series: kernel: Downgrade warning for unsafe parameters (rev2)
URL : https://patchwork.freedesktop.org/series/38614/
State : success
== Summary ==
Possible new issues:
Test kms_vblank:
Subgroup pipe-a-query-busy:
pass -> SKIP (shar
On Mon, 2018-02-26 at 18:31 +, Souza, Jose wrote:
> On Fri, 2018-02-23 at 19:12 -0800, Pandiyan, Dhinakaran wrote:
> > On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > > self, so lets use the mutex r
Quoting Daniele Ceraolo Spurio (2018-02-26 16:57:11)
>
>
> On 25/02/18 22:17, Sagar Arun Kamble wrote:
> >
> >
> > On 2/23/2018 10:31 PM, Daniele Ceraolo Spurio wrote:
> >>
> >>
> >> On 23/02/18 06:04, Michal Wajdeczko wrote:
> >>> Right after GPU reset there will be a small window of time duri
On underrun situations and SAGV enabled we can face hard hangs.
So let's reuse the FBC workaround and expand that to SAGV
on the hope that it is not already too late for that.
Cc: Paulo Zanoni
Cc: Ashar Shaikh
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
Now that we are spreading the places we can manipulate
sagv status let's protect it.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 15 +--
drivers/gpu/drm/i915/intel_pm.c | 41 ++---
2 files changed, 35 insertions(+), 21 deletio
We never used this information on upper level.
So let's just print the error and make the functions void.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 26 +++---
2 files changed, 13 insertions(+), 17 deletions(
This underrun work can be useful to disable more pm
function that can cause trouble on underrun situations,
like SAGV.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h| 7 +++-
drivers/gpu/drm/i915/i915_irq.c| 2 ++
drivers/gpu/drm/i915/
Quoting Chris Wilson (2018-02-24 18:54:04)
> If the specified object can not fit into the GTT due to overlap with a
> neighbouring pinned object (not part of the execobjects[]), we expect to
> fail with ENOSPC (as we cannot evict, rather than EINVAL for the user
> error in a badly constructed execo
Quoting Rodrigo Vivi (2018-02-26 20:53:08)
> -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
> -{
> - struct intel_fbc *fbc = &dev_priv->fbc;
> -
> - if (!fbc_supported(dev_priv))
> - return;
> -
> - /* There's no guarantee that underrun_d
Quoting Rodrigo Vivi (2018-02-26 20:53:07)
> Now that we are spreading the places we can manipulate
> sagv status let's protect it.
This needs a lot more information about the protection you need. "sagv
status" is too similar to sagv_status, so it seems like you are simply
talking about protecting
On Mon, Feb 26, 2018 at 08:54:47PM +, Chris Wilson wrote:
> Quoting Chris Wilson (2018-02-24 18:54:04)
> > If the specified object can not fit into the GTT due to overlap with a
> > neighbouring pinned object (not part of the execobjects[]), we expect to
> > fail with ENOSPC (as we cannot evict
== Series Details ==
Series: series starting with [1/4] drm/i915: Don't propagate SAGV errnos in
vain.
URL : https://patchwork.freedesktop.org/series/38987/
State : failure
== Summary ==
Applying: drm/i915: Don't propagate SAGV errnos in vain.
error: sha1 information is lacking or useless
(d
Quoting Ville Syrjälä (2018-02-26 21:22:03)
> On Mon, Feb 26, 2018 at 08:54:47PM +, Chris Wilson wrote:
> > Quoting Chris Wilson (2018-02-24 18:54:04)
> > > If the specified object can not fit into the GTT due to overlap with a
> > > neighbouring pinned object (not part of the execobjects[]), w
When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.
Reference:
https://01.org/sites/default/files/documentation/intel-gfx-p
v2
- removed the PSR dependency, now getting lock all the times when available
- renamed functions to avoid nested calls
- moved register bits right after the DP_AUX_CH_MUTEX()
- removed 'drm/i915: keep AUX powered while PSR is enabled' Dhinakaran Pandiyan
will sent a better and final version
v3
-
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Fill preempt context once
at init time
URL : https://patchwork.freedesktop.org/series/38975/
State : success
== Summary ==
Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-a
On Mon, Feb 26, 2018 at 09:21:19PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-02-26 20:53:07)
> > Now that we are spreading the places we can manipulate
> > sagv status let's protect it.
>
> This needs a lot more information about the protection you need. "sagv
> status" is too simila
== Series Details ==
Series: HDCP1.4 fixes
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
Known issues:
Test kms_cursor_legacy:
Subgroup short-flip-after-cursor-atomic-transitions-varying-size:
pass -> SKIP (shard-s
On Mon, Feb 26, 2018 at 09:00:50PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-02-26 20:53:08)
> > -void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_fbc *fbc = &dev_priv->fbc;
> > -
> > - if (!fbc_supported(dev_priv))
> > -
== Series Details ==
Series: drm/i915: Add and enable DP AUX CH mutex (rev3)
URL : https://patchwork.freedesktop.org/series/38655/
State : success
== Summary ==
Series 38655v3 drm/i915: Add and enable DP AUX CH mutex
https://patchwork.freedesktop.org/api/1.0/series/38655/revisions/3/mbox/
---
On Mon, Feb 26, 2018 at 01:48:37PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separ
== Series Details ==
Series: drm/i915: expose RCS topology to userspace (rev2)
URL : https://patchwork.freedesktop.org/series/38981/
State : success
== Summary ==
Possible new issues:
Test pm_sseu:
Subgroup full-enable:
pass -> FAIL (shard-apl)
K
Quoting Ramalingam C (2018-02-26 17:12:39)
> DP and HDMI HDCP specifications are varying with respect to
> detecting the R0 and ksv_fifo availability.
>
> DP will produce CP_IRQ and set a bit for indicating the R0 and
> FIFO_READY status.
>
> Whereas HDMI will set a bit for FIFO_READY but there i
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that de
On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
On 2/23/2018 4:35 AM, Oscar Mateo wrote:
+ * We might have detected that some engines are fused off after we
initialized
+ * the forcewake domains. Prune them, to make sure they only
reference existing
+ * engines.
+ */
+void intel_uncore
On Fri, Feb 23, 2018 at 04:40:38PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > Host/Render modifications do not trigger PSR exit
> > or Wireless quick capture exit correctly.
> >
>
> I don't get this workaround either. The wording indicates fron
On Fri, Feb 23, 2018 at 04:24:35PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> > the CPU host modify writes may not get updated on the Display
> > as expected.
> > WA: Write 0x
On Fri, Feb 23, 2018 at 03:46:09PM -0800, Pandiyan, Dhinakaran wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > It is a fact that scheduled work is now improved.
> >
> > But it is also a fact that on core platforms that shouldn't
> > be needed. We only need to actually wait on V
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