Re: [Intel-gfx] [PATCH 5/5] drm/i915: Call prepare/finish around intel_gpu_reset() during GEM sanitize

2018-03-02 Thread Mika Kuoppala
Chris Wilson writes: > During GEM sanitization, we reset the GPU so that it's always in a > default state whenever we take over or return the GPU back to the BIOS. > We call the GPU reset directly, so that we don't get caught up in trying > to handle GEM or KMS state

[Intel-gfx] [PATCH 5/6] drm/i915/icl: Add Indirect Context Offset for Gen11

2018-03-02 Thread Mika Kuoppala
From: Michel Thierry v2: rebased to intel_lr_indirect_ctx_offset v3: rebase, move define to intel_lrc_reg.h BSpec: 11740 Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko

[Intel-gfx] [PATCH 1/6] drm/i915/icl: Ringbuffer interrupt handling

2018-03-02 Thread Mika Kuoppala
From: Tvrtko Ursulin On Gen11 interrupt masks need to be clear to allow C6 entry. We keep them all enabled knowing that we generate extra interrupts. v2: Rebase. v3: Remove gen 11 extra check in logical_render_ring_init. v4: Rebase fixes. v5: Rebase/refactor. v6:

[Intel-gfx] [PATCH 3/6] drm/i915/icl: new context descriptor support

2018-03-02 Thread Mika Kuoppala
From: Daniele Ceraolo Spurio Starting from Gen11 the context descriptor format has been updated in the HW. The hw_id field has been considerably reduced in size and engine class and instance fields have been added. There is a slight name clashing issue because

[Intel-gfx] [PATCH 6/6] drm/i915/icl: Gen11 forcewake support

2018-03-02 Thread Mika Kuoppala
From: Daniele Ceraolo Spurio The main difference with previous GENs is that starting from Gen11 each VCS and VECS engine has its own power well, which only exist if the related engine exists in the HW. The fallback forcewake request workaround is only needed on

[Intel-gfx] [PATCH 4/6] drm/i915/icl: Enhanced execution list support

2018-03-02 Thread Mika Kuoppala
From: Thomas Daniel Enhanced Execlists is an upgraded version of execlists which supports up to 8 ports. The lrcs to be submitted are written to a submit queue (the ExecLists Submission Queue - ELSQ), which is then loaded on the HW. When writing to the ELSP register, the

[Intel-gfx] [PATCH 2/6] drm/i915/icl: Correctly initialize the Gen11 engines

2018-03-02 Thread Mika Kuoppala
From: Oscar Mateo Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio base definitions for all of them. Bspec: 20944 Bspec: 7021 v2: Set the correct mmio_base in intel_engines_init_mmio; updating the base mmio values any later would cause incorrect reads

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm: Don't create properties without names (rev2)

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm: Don't create properties without names (rev2) URL : https://patchwork.freedesktop.org/series/39277/ State : success == Summary == Known issues: Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-bottom-edge:

Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

2018-03-02 Thread Mika Kuoppala
Chris Wilson writes: > During reset/wedging, we have to clean up the requests on the timeline > and flush the pending interrupt state. Currently, we are abusing the irq > disabling of the timeline spinlock to protect the irq state in > conjunction to the engine's

Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

2018-03-02 Thread Chris Wilson
Quoting Mika Kuoppala (2018-03-02 15:50:53) > Chris Wilson writes: > > > During reset/wedging, we have to clean up the requests on the timeline > > and flush the pending interrupt state. Currently, we are abusing the irq > > disabling of the timeline spinlock to protect

Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Keep the AKSV details in intel_dp_hdcp_write_an_aksv()

2018-03-02 Thread Ville Syrjälä
On Fri, Feb 23, 2018 at 08:14:53PM +0530, Ramalingam C wrote: > > > On Friday 23 February 2018 07:16 PM, Ville Syrjälä wrote: > > On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote: > >> This is really making it cleaner. > >> > >> Reviewed-by: Ramalingam C > >>

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling URL : https://patchwork.freedesktop.org/series/39293/ State : success == Summary == Series 39293v1 series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling

[Intel-gfx] [PATCH 1/1] intel: align reuse buffer's size on page size instead

2018-03-02 Thread James Xiong
From: "Xiong, James" With gem_reuse enabled, when a buffer size is different than the sizes of buckets, it is aligned to the next bucket's size, which means about 25% more memory than the requested is allocated in the worst senario. For example: Orignal sizeActual

[Intel-gfx] [PATCH libdrm 1/1] intel: allocate buffer with the requested size when reuse is disabled

2018-03-02 Thread James Xiong
From: "Xiong, James" Previously a bucket size was used for buffer allocation whether bo_reuse is false or true. This patch returns NULL in function drm_intel_gem_bo_bucket_for_size() when bo_reuse is false, the original requested size is used instead. Signed-off-by:

Re: [Intel-gfx] i915 vs checkpatch

2018-03-02 Thread Jani Nikula
On Thu, 01 Mar 2018, Jani Nikula wrote: > Does checkpatch support disabling checks or do you have to filter them > out from the output? Turns out it does. There's an --ignore option. For starters, I sent a patch [1] to show the warning types in the output, so we can

[Intel-gfx] ✗ Fi.CI.IGT: warning for Documentation patch for batchbuffer submission (rev2)

2018-03-02 Thread Patchwork
== Series Details == Series: Documentation patch for batchbuffer submission (rev2) URL : https://patchwork.freedesktop.org/series/38433/ State : warning == Summary == Possible new issues: Test gem_pwrite: Subgroup big-gtt-forwards: pass -> SKIP

[Intel-gfx] [PATCH v2 12/14] drm/i915: Clean up DP pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Clean up the DP pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state(), the port state asserts, and the VLV power sequencer code. v2: Return PIPE_A for cpt/ppt when the port

[Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

2018-03-02 Thread Chris Wilson
A couple of bugs inside the hang injector, the worst being that the presumed_offset of the reloc didn't match the batch; so if the reloc was skipped (as the presumed_offset matched the reloc offset), the batch wasn't updated and so we may not have generated a hanging batch at all! Secondly, the

Re: [Intel-gfx] [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

2018-03-02 Thread Yaodong Li
On 03/02/2018 12:04 AM, Sagar Arun Kamble wrote:  (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED) + +/** + * intel_wopcm_init_early() - Early initialization of the WOPCM. + * @wopcm: pointer to intel_wopcm. + * + * Setup the size of WOPCM which will be used by later on WOPCM partitioning. + */

Re: [Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

2018-03-02 Thread Mika Kuoppala
Chris Wilson writes: > Quoting Mika Kuoppala (2018-03-02 15:50:53) >> Chris Wilson writes: >> >> > During reset/wedging, we have to clean up the requests on the timeline >> > and flush the pending interrupt state. Currently, we are abusing

Re: [Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

2018-03-02 Thread Ville Syrjälä
On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote: > A couple of bugs inside the hang injector, the worst being that the > presumed_offset of the reloc didn't match the batch; so if the reloc was > skipped (as the presumed_offset matched the reloc offset), the batch > wasn't updated and

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset (rev2)

2018-03-02 Thread Imre Deak
On Thu, Mar 01, 2018 at 10:48:25PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset (rev2) > URL : https://patchwork.freedesktop.org/series/39129/ > State : success > > == Summary == Thanks for the review, pushed it to

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: clean up leftover references to CHV HBR2 support

2018-03-02 Thread Patchwork
== Series Details == Series: drm/i915/dp: clean up leftover references to CHV HBR2 support URL : https://patchwork.freedesktop.org/series/39285/ State : success == Summary == Series 39285v1 drm/i915/dp: clean up leftover references to CHV HBR2 support

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure URL : https://patchwork.freedesktop.org/series/39280/ State : failure == Summary == Possible new issues: Test drv_missed_irq: pass -> SKIP

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Stop engines around GPU reset preparations

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/5] drm/i915: Stop engines around GPU reset preparations URL : https://patchwork.freedesktop.org/series/39284/ State : failure == Summary == Possible new issues: Test drv_selftest: Subgroup live_hangcheck: pass

Re: [Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

2018-03-02 Thread Rodrigo Vivi
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > DisplayPort Phy compliance test patterns register definitions. Hi Clint, what's the current plan to add the actual use of these registers and bits? thanks, Rodrigo.

Re: [Intel-gfx] [PATCH] drm/i915: Register definitions for DP Phy compiance

2018-03-02 Thread Clint Taylor
On 03/02/2018 10:10 AM, Rodrigo Vivi wrote: On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote: From: Clint Taylor DisplayPort Phy compliance test patterns register definitions. Hi Clint, what's the current plan to add the actual use of

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up the port pipe select bits (rev2)

2018-03-02 Thread Patchwork
== Series Details == Series: drm/i915: Clean up the port pipe select bits (rev2) URL : https://patchwork.freedesktop.org/series/39259/ State : failure == Summary == Series 39259v2 drm/i915: Clean up the port pipe select bits

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index URL : https://patchwork.freedesktop.org/series/39305/ State : success == Summary == Series 39305v1 series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

2018-03-02 Thread Patchwork
== Series Details == Series: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset URL : https://patchwork.freedesktop.org/series/38678/ State : failure == Summary == Applying: drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

[Intel-gfx] [PATCH 2/3] drm/i915/error: standardize function style in error capture

2018-03-02 Thread Daniele Ceraolo Spurio
some of the static functions used from capture() have the "i915_" prefix while other don't; most of them take i915 as a parameter, but one of them derives it internally from error->i915. Let's be consistent by avoiding prefix for static functions and always providing i915 as a parameter.

[Intel-gfx] [PATCH 3/3] drm/i915/error: capture uc_state after gen_state

2018-03-02 Thread Daniele Ceraolo Spurio
error->device_info.has_guc, which we check in capture_uc_state, is set in capture_gen_state, so the latter needs to be performed first. Reported-by: Vinay Belgaumkar Cc: Vinay Belgaumkar Cc: Michal Wajdeczko

[Intel-gfx] [PATCH 1/3] drm/i915/error: remove unused gen8_engine_sync_index

2018-03-02 Thread Daniele Ceraolo Spurio
Leftover from Gen8 ringbuffer support removal Cc: Chris Wilson Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_gpu_error.c | 21 - 1 file changed, 21 deletions(-) diff --git

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/6] drm/i915/icl: Ringbuffer interrupt handling URL : https://patchwork.freedesktop.org/series/39293/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-contexts: incomplete -> PASS

Re: [Intel-gfx] [PATCH 2/3] drm/i915/error: standardize function style in error capture

2018-03-02 Thread Michal Wajdeczko
On Fri, 02 Mar 2018 20:19:29 +0100, Daniele Ceraolo Spurio wrote: some of the static functions used from capture() have the "i915_" prefix while other don't; most of them take i915 as a parameter, but one of them derives it internally from error->i915. Let's

Re: [Intel-gfx] [PATCH igt] lib: Fix MI_BATCH_BUFFER_START for hang injection

2018-03-02 Thread Chris Wilson
Quoting Ville Syrjälä (2018-03-02 17:09:29) > On Fri, Mar 02, 2018 at 04:13:46PM +, Chris Wilson wrote: > > A couple of bugs inside the hang injector, the worst being that the > > presumed_offset of the reloc didn't match the batch; so if the reloc was > > skipped (as the presumed_offset

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: clean up leftover references to CHV HBR2 support

2018-03-02 Thread Patchwork
== Series Details == Series: drm/i915/dp: clean up leftover references to CHV HBR2 support URL : https://patchwork.freedesktop.org/series/39285/ State : success == Summary == Known issues: Test gem_eio: Subgroup in-flight-contexts: pass -> INCOMPLETE

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging URL : https://patchwork.freedesktop.org/series/39312/ State : warning == Summary == Possible new issues: Test kms_frontbuffer_tracking: Subgroup

Re: [Intel-gfx] [PULL] drm-misc-next

2018-03-02 Thread Sean Paul
On Wed, Feb 28, 2018 at 3:34 PM, Sean Paul wrote: > > Hi Dave, > Here's this weeks pull, relatively small when you pull out the trivial fixes. > > drm-misc-next-2018-02-28: > drm-misc-next for 4.17: > > UAPI Changes: > Fix drm_color_ctm matrix docs to match usage and

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

2018-03-02 Thread Pandiyan, Dhinakaran
On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote: > On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote: > > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote: > > > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote: > > > > On Tue, 2018-02-27 at 23:34 +0200, Ville

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

2018-03-02 Thread Rodrigo Vivi
Ville Syrjälä writes: > On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote: >> On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote: >> > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote: >> > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [CI,1/3] drm/i915: Suspend submission tasklets around wedging URL : https://patchwork.freedesktop.org/series/39312/ State : success == Summary == Series 39312v1 series starting with [CI,1/3] drm/i915: Suspend submission tasklets around

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/error: remove unused gen8_engine_sync_index URL : https://patchwork.freedesktop.org/series/39305/ State : warning == Summary == Possible new issues: Test gem_pwrite: Subgroup big-gtt-forwards: pass

[Intel-gfx] [CI 1/3] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Chris Wilson
After staring hard at sequences like [ 28.199013] systemd-1 2..s. 26062228us : execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?] [ 28.199095] systemd-1 2..s. 26062229us : execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, active=0x1 [

[Intel-gfx] [CI 3/3] drm/i915/execlists: Split spinlock from its irq disabling side-effect

2018-03-02 Thread Chris Wilson
During reset/wedging, we have to clean up the requests on the timeline and flush the pending interrupt state. Currently, we are abusing the irq disabling of the timeline spinlock to protect the irq state in conjunction to the engine's timeline requests, but this is accidental and conflates the

[Intel-gfx] [CI 2/3] drm/i915/execlists: Move irq state manipulation inside irq disabled region

2018-03-02 Thread Chris Wilson
Although this state (execlists->active and engine->irq_posted) itself is not protected by the engine->timeline spinlock, it does conveniently ensure that irqs are disabled. We can use this to protect our manipulation of the state and so ensure that the next IRQ to arrive sees consistent state and

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

2018-03-02 Thread Rodrigo Vivi
On Fri, Mar 02, 2018 at 11:20:42PM +, Pandiyan, Dhinakaran wrote: > > > > On Thu, 2018-03-01 at 12:53 +0200, Ville Syrjälä wrote: > > On Wed, Feb 28, 2018 at 11:55:39PM +, Souza, Jose wrote: > > > On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote: > > > > On Wed, Feb 28, 2018 at

Re: [Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Chris Wilson
Quoting Ville Syrjälä (2018-03-02 08:27:45) > On Fri, Mar 02, 2018 at 08:12:35AM +, Chris Wilson wrote: > > Prevent the compiler from caching reads/writes to the hw register as we > > do want to perform mmio. > > > > Whilst fixing up the mmio access, also ensure that we do not leave the > >

Re: [Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

2018-03-02 Thread Jani Nikula
On Thu, 01 Mar 2018, Lyude Paul wrote: > Pushed with some small whitespace changes to make sparse happy, thanks! Please do not push patches before they've passed CI. This patch gives [1]: [ 281.167033] i915 :00:02.0: DP-2: EDID is invalid: ... [ 282.806393]

[Intel-gfx] [PATCH 04/14] drm/i915: Clean up TV pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Parametrize the TV pipe select bits. For consistency with the new way of doing things, let's read out the pipe select bits even when the port is disable, even though we don't need that behaviour for asserts in this case. Signed-off-by: Ville

[Intel-gfx] [PATCH 06/14] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these fall through the if ladder in a weird way. This function will look at the actual buf trans tables we have for HSW/BDW to determine the max vswing level. It looks to me like

[Intel-gfx] [PATCH 02/14] drm/i915: Clean up LVDS pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Clean up the LVDS pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 01/14] drm/i915: Clean up ADPA pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Clean up the ADPA pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 03/14] drm/i915: Clean up SDVO pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Clean up the SDVO pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 07/14] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä All DDI platforms support the full set of preemph settings for each supported vswing, so let's use the same code for them. We'll also move the code into intel_ddi.c so that it sits closer to the actual buf trans tables. Signed-off-by: Ville

[Intel-gfx] [PATCH 05/14] drm/i915: Clean up DVO pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Parametrize the DVO pipe select bits. For consistency with the new way of doing things, let's read out the pipe select bits even when the port is disable, even though we don't need that behaviour for asserts in this case. Signed-off-by: Ville

[Intel-gfx] [PATCH 00/14] drm/i915: Clean up the port pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä A bit of an effort to rid outselves of PORT_TO_PIPE() & co. The idea with those macros was to share them between all the port registers, but since not all port registers follow the same bit layout they're kinda just making it harder to see what

Re: [Intel-gfx] [RFC][PATCH 04/11] drm: Split the display info into static and dynamic parts

2018-03-02 Thread Linus Walleij
On Tue, Feb 27, 2018 at 1:56 PM, Ville Syrjala wrote: > From: Ville Syrjälä > > Currently we have a mix of static and dynamic information stored in > the display info structure. That makes it rather difficult to repopulate > the

[Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Chris Wilson
Prevent the compiler from caching reads/writes to the hw register as we do want to perform mmio. Whilst fixing up the mmio access, also ensure that we do not leave the test with any other bits still set in the forcewake register to prevent affecting other tests, as spotted by Tvrtko.

[Intel-gfx] [PATCH i-g-t v2] tests/gen7_forcewake_mt: Fix test

2018-03-02 Thread Tvrtko Ursulin
From: Tvrtko Ursulin 1. We need to tell the compiler mmio access cannot be optimized away (volatile). 2. We need to ensure we don't exit with forcewake left on. Signal threads to exit in a controlled fashion and install atexit handler just in case. v2: Do not assert

Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

2018-03-02 Thread Chris Wilson
Quoting Sagar Arun Kamble (2018-03-01 16:45:45) > GuC load function is named intel_guc_fw_upload() and HuC load function is > named intel_huc_init_hw(). Make them consistent intel_*_fw_upload. Also > move HuC fw loading functions and declarations to separate files > intel_huc_fw.c|h like GuC. > >

Re: [Intel-gfx] please do *NOT* backport 9965db26ac05 ("drm/i915: Check for fused or unused pipes")

2018-03-02 Thread Jani Nikula
On Thu, 15 Feb 2018, Greg KH wrote: > On Wed, Feb 14, 2018 at 06:22:56PM +0200, Jani Nikula wrote: >> >> Stable team, >> >> commit 9965db26ac05 ("drm/i915: Check for fused or unused pipes") >> >> with Cc: stable is broken, please do not backport. > > Ok, now dropped from my

Re: [Intel-gfx] i915 vs checkpatch

2018-03-02 Thread Joonas Lahtinen
Quoting Rodrigo Vivi (2018-03-01 20:00:07) > On Thu, Mar 01, 2018 at 06:13:31PM +0200, Jani Nikula wrote: > > > > I went through the recent checkpatch reports, and here's my take. > > > > On Thu, 01 Mar 2018, Arkadiusz Hiler wrote: > > > 2. Which of the checkpatch

[Intel-gfx] [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä AFAIK CHV was supposed to have HBR2 originally, but in the end the feature was dropped. We still have some code leftovers from those early days. Eliminate them. The extra bit for the training pattern seems to be dead in the hardware. I can set

Re: [Intel-gfx] [PATCH igt v2] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Ville Syrjälä
On Fri, Mar 02, 2018 at 08:12:35AM +, Chris Wilson wrote: > Prevent the compiler from caching reads/writes to the hw register as we > do want to perform mmio. > > Whilst fixing up the mmio access, also ensure that we do not leave the > test with any other bits still set in the forcewake

Re: [Intel-gfx] [PATCH v3 1/1] drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric

2018-03-02 Thread Chris Wilson
Quoting Sagar Arun Kamble (2018-03-01 16:45:45) > +static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) > +{ > + struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw); > + struct drm_i915_private *dev_priv = huc_to_i915(huc); > + unsigned long

[Intel-gfx] [CI i-g-t v3] don't look

2018-03-02 Thread Tvrtko Ursulin
From: Tvrtko Ursulin 1. We need to tell the compiler mmio access cannot be optimized away (volatile). 2. We need to ensure we don't exit with forcewake left on. Signal threads to exit in a controlled fashion and install atexit handler just in case. v2: Do not assert

Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_pm: Restore runtime pm state on test exit

2018-03-02 Thread Imre Deak
On Wed, Feb 28, 2018 at 03:35:06PM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Some tests (the ones which call igt_setup_runtime_pm and > igt_pm_enable_audio_runtime_pm) change default system configuration and > never restore it. > > The configured runtime

[Intel-gfx] [PATCH i-g-t v3] lib/igt_pm: Restore runtime pm state on test exit

2018-03-02 Thread Tvrtko Ursulin
From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and igt_pm_enable_audio_runtime_pm) change default system configuration and never restore it. The configured runtime suspend is aggressive and may influence behaviour of subsequent tests, so it

Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_pm: Restore runtime pm state on test exit

2018-03-02 Thread Tvrtko Ursulin
On 02/03/2018 09:29, Imre Deak wrote: On Wed, Feb 28, 2018 at 03:35:06PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and igt_pm_enable_audio_runtime_pm) change default system configuration and never restore

[Intel-gfx] [PATCH 08/14] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Almost all of the GEN7 checks in the DP code are actually looking for IVB. HSW doesn't even take these codepaths, and VLV is excluded on account of not having port A. So let's change the checks to IS_IVB to make the code less confusing.

[Intel-gfx] [PATCH 11/14] drm/i915: Nuke intel_trans_dp_port_sel()

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic drivers. Let's throw out intel_trans_dp_port_sel() and replace it with intel_get_crtc_new_encoder() which looks the atomic state instead. Since we now have to call

[Intel-gfx] [PATCH 13/14] drm/i915: Allow eDP on port C in theory

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä The power sequencer has bits to allow DP C to be used for eDP. Currently we assume this will never happen, but I guess it could theoretically be a thing. MAke the code do the right thing in that case, and toss in a MISSING_CASE() for any other

[Intel-gfx] [PATCH 14/14] drm/i915: Implement the missing bits of assert_panel_unlocked()

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Add the missing eDP port handling into assert_panel_unlocked(). We now have intel_dp_port_enabled() which makes this trivial. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 17

[Intel-gfx] [PATCH 12/14] drm/i915: Clean up DP pipe select bits

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Clean up the DP pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state(), the port state asserts, and the VLV power sequencer code. Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 09/14] drm/i915: Move intel_ddi_get_crtc_new_encoder() out from ddi code

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it elsewhere where we have some users left. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 29

[Intel-gfx] [PATCH 10/14] drm/i915: Parametrize TRANS_DP_PORT_SEL

2018-03-02 Thread Ville Syrjala
From: Ville Syrjälä Parametrize the TRANS_DP_PORT_SEL macros. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 8 +++- drivers/gpu/drm/i915/intel_display.c | 23 +++ 2 files changed,

Re: [Intel-gfx] [PATCH v12 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

2018-03-02 Thread Sagar Arun Kamble
On 3/2/2018 5:46 AM, Jackie Li wrote: GuC related exported functions should start with "intel_guc_" prefix and pass intel_guc as the first parameter since its GuC related. Current guc_ggtt_offset() failed to follow this code convention and this is a problem for future patches that needs to

Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Update PSR2 resolution check for Cannonlake

2018-03-02 Thread Ville Syrjälä
On Thu, Mar 01, 2018 at 10:04:04PM +, Pandiyan, Dhinakaran wrote: > > > > On Thu, 2018-03-01 at 23:47 +0200, Ville Syrjälä wrote: > > On Thu, Mar 01, 2018 at 01:27:09PM -0800, Dhinakaran Pandiyan wrote: > > > In fact, apply the Cannonlake resolution check for all >= Gen-10 platforms > > >

Re: [Intel-gfx] [PATCH v12 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

2018-03-02 Thread Sagar Arun Kamble
On 3/2/2018 5:46 AM, Jackie Li wrote: Hardware may have specific restrictions on GuC WOPCM offset and size. On Gen9, the value of the GuC WOPCM size register needs to be larger than the value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for reserved GuC WOPCM. Fail to enforce

[Intel-gfx] [PATCH igt v3] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Chris Wilson
Prevent the compiler from caching reads/writes to the hw register as we do want to perform mmio. Whilst fixing up the mmio access, also ensure that we do not leave the test with any other bits still set in the forcewake register to prevent affecting other tests, as spotted by Tvrtko.

[Intel-gfx] [PATCH igt v4] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Chris Wilson
Prevent the compiler from caching reads/writes to the hw register as we do want to perform mmio. Whilst fixing up the mmio access, also ensure that we do not leave the test with any other bits still set in the forcewake register to prevent affecting other tests, as spotted by Tvrtko.

[Intel-gfx] [PATCH 3/5] drm/i915/execlists: Move irq state manipulation inside irq disabled region

2018-03-02 Thread Chris Wilson
Although this state (execlists->active and engine->irq_posted) itself is not protected by the engine->timeline spinlock, it does conveniently ensure that irqs are disabled. We can use this to protect our manipulation of the state and so ensure that the next IRQ to arrive sees consistent state and

[Intel-gfx] [PATCH 1/5] drm/i915: Stop engines around GPU reset preparations

2018-03-02 Thread Chris Wilson
As we make preparations to reset the GPU state, we assume that the GPU is hung and will not advance. Make this assumption more explicit by setting the STOP_RING bit on the engines as part of our early reset preparations. Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [PATCH 5/5] drm/i915: Call prepare/finish around intel_gpu_reset() during GEM sanitize

2018-03-02 Thread Chris Wilson
During GEM sanitization, we reset the GPU so that it's always in a default state whenever we take over or return the GPU back to the BIOS. We call the GPU reset directly, so that we don't get caught up in trying to handle GEM or KMS state that is isn't ready at that time, but now we have a couple

[Intel-gfx] [PATCH 2/5] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Chris Wilson
After starting hard at sequences like [ 28.199013] systemd-1 2..s. 26062228us : execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?] [ 28.199095] systemd-1 2..s. 26062229us : execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, active=0x1 [

[Intel-gfx] [PATCH 4/5] drm/i915/execlists: Split spinlock from its irq disabling side-effect

2018-03-02 Thread Chris Wilson
During reset/wedging, we have to clean up the requests on the timeline and flush the pending interrupt state. Currently, we are abusing the irq disabling of the timeline spinlock to protect the irq state in conjunction to the engine's timeline requests, but this is accidental and conflates the

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/uc: Introduce intel_uc_suspend|resume

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [v2,1/2] drm/i915/uc: Introduce intel_uc_suspend|resume URL : https://patchwork.freedesktop.org/series/39272/ State : failure == Summary == Possible new issues: Test drv_missed_irq: pass -> SKIP (shard-apl)

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth failure URL : https://patchwork.freedesktop.org/series/39280/ State : success == Summary == Series 39280v1 series starting with [v2,1/2] drm/i915/huc: Mark firmware as failed on auth

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Mika Kuoppala
Chris Wilson writes: > After starting hard at sequences like Perhaps you meant staring, but starting is fine too. -Mika > > [ 28.199013] systemd-1 2..s. 26062228us : > execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?] > [ 28.199095]

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm: Don't create properties without names (rev2)

2018-03-02 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm: Don't create properties without names (rev2) URL : https://patchwork.freedesktop.org/series/39277/ State : success == Summary == Series 39277v2 series starting with [1/3] drm: Don't create properties without names

[Intel-gfx] [PATCH] drm/i915/dp: clean up leftover references to CHV HBR2 support

2018-03-02 Thread Jani Nikula
No such thing as CHV HBR2. Clean up after commit ed63baaf849e ("drm/i915: Avoid TP3 on CHV"). Reported-by: Ville Syrjälä Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dp.c | 2 --

Re: [Intel-gfx] i915 vs checkpatch

2018-03-02 Thread Jani Nikula
On Fri, 02 Mar 2018, Joonas Lahtinen wrote: > Quoting Rodrigo Vivi (2018-03-01 20:00:07) >> On Thu, Mar 01, 2018 at 06:13:31PM +0200, Jani Nikula wrote: >> > >> > I went through the recent checkpatch reports, and here's my take. >> > >> > On Thu, 01 Mar 2018,

[Intel-gfx] [PATCH igt v5] igt/gen7_forcewake_mt: Make the mmio register as volatile

2018-03-02 Thread Chris Wilson
Prevent the compiler from caching reads/writes to the hw register as we do want to perform mmio. Whilst fixing up the mmio access, also ensure that we do not leave the test with any other bits still set in the forcewake register to prevent affecting other tests, as spotted by Tvrtko. v2: Use

Re: [Intel-gfx] [PATCH v3 05/10] pwm: add PWM mode to pwm_config()

2018-03-02 Thread Claudiu Beznea
On 28.02.2018 22:04, Jani Nikula wrote: > On Wed, 28 Feb 2018, Thierry Reding wrote: >> Anyone that needs something other than normal mode should use the new >> atomic PWM API. > > At the risk of revealing my true ignorance, what is the new atomic PWM > API? Where?

Re: [Intel-gfx] [PATCH 01/15] drm/i915/guc: Tidy guc_log_control

2018-03-02 Thread Sagar Arun Kamble
On 2/27/2018 6:22 PM, Michał Winiarski wrote: We plan to decouple log runtime (mapping + relay) from verbosity control. Let's tidy the code now to reduce the churn in the following patches. Signed-off-by: Michał Winiarski Cc: Chris Wilson

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Kill the remaining CHV HBR2 leftovers

2018-03-02 Thread Patchwork
== Series Details == Series: drm/i915: Kill the remaining CHV HBR2 leftovers URL : https://patchwork.freedesktop.org/series/39260/ State : success == Summary == Series 39260v1 drm/i915: Kill the remaining CHV HBR2 leftovers

[Intel-gfx] [PATCH] drm/i915: Stop engines around GPU reset preparations

2018-03-02 Thread Chris Wilson
As we make preparations to reset the GPU state, we assume that the GPU is hung and will not advance. Make this assumption more explicit by setting the STOP_RING bit on the engines as part of our early reset preparations. Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [PATCH 1/2] drm/i915: Stop engines around GPU reset preparations

2018-03-02 Thread Chris Wilson
As we make preparations to reset the GPU state, we assume that the GPU is hung and will not advance. Make this assumption more explicit by setting the STOP_RING bit on the engines as part of our early reset preparations. Signed-off-by: Chris Wilson Cc: Mika Kuoppala

[Intel-gfx] [PATCH 2/2] drm/i915: Suspend submission tasklets around wedging

2018-03-02 Thread Chris Wilson
After starting hard at sequences like [ 28.199013] systemd-1 2..s. 26062228us : execlists_submission_tasklet: rcs0 cs-irq head=0 [0?], tail=1 [1?] [ 28.199095] systemd-1 2..s. 26062229us : execlists_submission_tasklet: rcs0 csb[1]: status=0x0018:0x, active=0x1 [

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