Since Haswell we have no color range indication either in the pipe or
port registers for DP. Instead, there's a separate register for setting
the DP Main Stream Attributes (MSA) directly. The MSA register
definition makes no references to colorimetry, just a vague reference to
the DP spec. The
== Series Details ==
Series: drm/i915: set DP Main Stream Attribute for color range on DDI platforms
URL : https://patchwork.freedesktop.org/series/48145/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4664_full -> Patchwork_9933_full =
== Summary - SUCCESS ==
No
Hi Jani, Daniel
Could you help to comment? thanks,
- Feng
On Thu, Jul 12, 2018 at 03:51:34PM +0800, Feng Tang wrote:
> Hi Daniel,
>
> On Thu, Jul 12, 2018 at 08:54:34AM +0200, Daniel Vetter wrote:
> > On Thu, Jul 12, 2018 at 09:29:01AM +0800, Feng Tang wrote:
> > > On Tue, Jun 26, 2018 at
== Series Details ==
Series: drm/i915: set DP Main Stream Attribute for color range on DDI platforms
URL : https://patchwork.freedesktop.org/series/48145/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4664 -> Patchwork_9933 =
== Summary - SUCCESS ==
No regressions
Quoting Patchwork (2018-08-14 16:53:29)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/execlists: Clear STOP_RING bit
> before restoring the context
> URL : https://patchwork.freedesktop.org/series/48195/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes
== Series Details ==
Series: Increase LSPCON timeout
URL : https://patchwork.freedesktop.org/series/48183/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4665_full -> Patchwork_9937_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are
On Fri, Aug 03, 2018 at 12:07:43PM +0300, Petri Latvala wrote:
> On Thu, Aug 02, 2018 at 03:09:37PM -0700, Lucas De Marchi wrote:
> > I was grepping for shard as the tests run on CI, but the only occurrence
> > was this one which seems to be a typo since it's about prime tests.
> >
> > Fixes:
Quoting Patchwork (2018-08-14 18:48:08)
> == Series Details ==
>
> Series: drm/i915: Clear stop-engine for a pardoned reset
> URL : https://patchwork.freedesktop.org/series/48202/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4666 -> Patchwork_9943 =
>
> ==
On Fri, Jul 27, 2018 at 12:36:47PM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
== Series Details ==
Series: drm/i915/execlists: Clear STOP_RING bit before restoring the context
URL : https://patchwork.freedesktop.org/series/48187/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4665_full -> Patchwork_9938_full =
== Summary - SUCCESS ==
No
If we pardon a per-engine reset, we may leave the STOP_RING bit asserted
in RING_MI_MODE resulting in the engine hanging. Unconditionally clear
it on the per-engine exit path as we know that either we skipped the
reset and so need the cancellation, or the reset was successful and the
cancellation
On 14/08/2018 16:27, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-14 16:21:08)
On 14/08/2018 16:09, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-14 16:05:13)
From: Tvrtko Ursulin
Notice in more places if we are running behind.
Signed-off-by: Tvrtko Ursulin
---
On 14/08/18 17:05, Lionel Landwerlin wrote:
On 14/08/18 16:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-14 16:11:36)
On 14/08/18 15:59, Chris Wilson wrote:
And I'd still recommend not using indirect access if we can apply the
changes immediately.
-Chris
Hangs on Gen9 :(
How
== Series Details ==
Series: drm/i915: Clear stop-engine for a pardoned reset
URL : https://patchwork.freedesktop.org/series/48202/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4666 -> Patchwork_9943 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Quoting Antonio Argenziano (2018-08-10 19:11:02)
>
>
> On 10/08/18 10:51, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2018-08-10 18:41:22)
> >> How does the test fail if the sync goes wrong? Hang detector on the
> >> queued batch?
> >
> > We have a hang detector for both missed wakeups
On 14/08/18 11:27, Chris Wilson wrote:
Quoting Antonio Argenziano (2018-08-10 19:11:02)
On 10/08/18 10:51, Chris Wilson wrote:
Quoting Antonio Argenziano (2018-08-10 18:41:22)
How does the test fail if the sync goes wrong? Hang detector on the
queued batch?
We have a hang detector for
== Series Details ==
Series: drm/i915/execlists: Refind the active request before resetting
URL : https://patchwork.freedesktop.org/series/48190/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4666_full -> Patchwork_9939_full =
== Summary - WARNING ==
Minor unknown
Quoting Tvrtko Ursulin (2018-08-14 19:27:08)
> To not use it is to reimplement existing handy helpers - not ideal.
The problem was that they were overly handy so I tried to avoid them in
benchmarks/ after being burnt too often.
> To split the test bits from useful helpers sounds like quite a
Quoting Tvrtko Ursulin (2018-08-14 19:49:46)
>
> On 13/08/2018 10:16, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-08-13 10:11:44)
> >>
> >> On 13/08/2018 09:16, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-08-13 09:02:18)
> From: Lionel Landwerlin
>
> Abstract
== Series Details ==
Series: Icelake DMC v1.07
URL : https://patchwork.freedesktop.org/series/48207/
State : failure
== Summary ==
Patch is empty.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the
Add Support to load DMC on Icelake.
While at it, also add support to load the firmware
during system resume.
v2: load firmware during system resume.(Imre)
v3: enable has_csr for icelake.(Jyoti)
Cc: Jyoti Yadav
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Adding The pull request in the Cover leteer:
The following changes since commit fdd34681195afa70a63a9a6cf352513cf3b53896:
linux-firmware: add firmware for mt76x0 (2018-08-14 10:35:03 -0400)
are available in the git repository at:
git://anongit.freedesktop.org/git/drm/drm-firmware.git/
== Series Details ==
Series: Icelake DMC v1.07 (rev2)
URL : https://patchwork.freedesktop.org/series/48207/
State : failure
== Summary ==
Patch is empty.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the
On 13/08/2018 10:16, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-13 10:11:44)
On 13/08/2018 09:16, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-13 09:02:18)
From: Lionel Landwerlin
Abstract the context image access a bit.
Signed-off-by: Lionel Landwerlin
Reviewed-by:
On 14/08/2018 15:59, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-14 15:40:58)
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within
Adding The pull request in the Cover leteer:
The following changes since commit fdd34681195afa70a63a9a6cf352513cf3b53896:
linux-firmware: add firmware for mt76x0 (2018-08-14 10:35:03 -0400)
are available in the git repository at:
git://anongit.freedesktop.org/git/drm/drm-firmware.git/
Quoting Tvrtko Ursulin (2018-08-14 19:44:09)
>
> On 14/08/2018 15:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-08-14 15:40:58)
> >> From: Chris Wilson
> >>
> >> We want to allow userspace to reconfigure the subslice configuration for
> >> its own use case. To do so, we expose a
On Mon, 2018-08-13 at 22:19 +, Souza, Jose wrote:
> On Fri, 2018-07-27 at 13:04 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > PLLs are the source clocks for the DDIs so in order to determine
> > the
> > ddi clock we need to check the PLL configuration.
> >
> > For MG PHy Ports
== Series Details ==
Series: Per context dynamic (sub)slice power-gating
URL : https://patchwork.freedesktop.org/series/48194/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4666_full -> Patchwork_9941_full =
== Summary - FAILURE ==
Serious unknown changes coming with
Adding The pull request in the Cover leteer:
The following changes since commit fdd34681195afa70a63a9a6cf352513cf3b53896:
linux-firmware: add firmware for mt76x0 (2018-08-14 10:35:03 -0400)
are available in the git repository at:
git://anongit.freedesktop.org/git/drm/drm-firmware.git/
On Tue, 14 Aug 2018 11:34:07 +0200,
Daniel Vetter wrote:
>
> On Tue, Aug 14, 2018 at 02:54:31PM +0800, Feng Tang wrote:
> > Hi Jani, Daniel
> >
> > Could you help to comment? thanks,
> >
> > - Feng
> >
> > On Thu, Jul 12, 2018 at 03:51:34PM +0800, Feng Tang wrote:
> > > Hi Daniel,
> > >
> > >
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev11)
URL : https://patchwork.freedesktop.org/series/36068/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b96e44106d65 drm/i915: Introduce CRTC output format
2cc560ee9457 drm/i915: Add CRTC output
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev11)
URL : https://patchwork.freedesktop.org/series/36068/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4664 -> Patchwork_9934 =
== Summary - SUCCESS ==
No regressions found.
External URL:
This reapplies commit 39f3be162c46 ("drm/i915: Kick waiters on resetting
legacy rings") after the improved gem_eio was run across all machines we
found that gen3 and early gen4 still lost the immediate interrupt
following reset, and the HWSTAM w/a applied to gen6+ is inadequate.
Unlike the later
On Sun, Aug 12, 2018 at 11:03:41PM +0300, Haneen Mohammed wrote:
> So that this test can be run in drivers other than i915.
> Remove devid and only check it if the driver is i915.
>
> Signed-off-by: Haneen Mohammed
> ---
> tests/kms_cursor_crc.c | 31 +--
> 1 file
This patch series does the following:
- Adds concept of CRTC output format, which indicates if a CRTC is
driving RGB/YCBCR4:4:4/YCBCR4:2:0 or other outputs.
- Sets RGB as default output for all displays.
- Enables YCBCR4:4:4/4:2:0 outputs for LSPCON displays
- Drives these outputs on LSPCON
LSPCON chips can generate YCBCR outputs, if asked nicely :).
In order to generate YCBCR 4:2:0 outputs, a source must:
- send YCBCR 4:4:4 signals to LSPCON
- program color space as 4:2:0 in AVI infoframes
Whereas for YCBCR 4:4:4 outputs, the source must:
- send YCBCR 4:4:4 signals to LSPCON
-
Different LSPCON vendors specify their custom methods to pass
AVI infoframes to the LSPCON chip, so does Parade tech.
This patch adds functions to arrange and write AVI infoframes
into Parade LSPCON chips.
V2: rebase
V3: Added r-b from Maarten
V4: rebase
V5: rebase
V6: rebase
V7: Fixed
In order to pass AVI infoframes to LSPCON devices, a source has to
write them in a vendor recommended method and location.
This patch series:
- adds generic LSPCON infoframe setup functions.
- registers these functions into existing AVI infoframe framework.
- triggers these functions from modeset
From: "Sharma, Shashank"
Intel LSPCON chip is provided by 2 vendors:
- Megachips America (MCA)
- Parade technologies (Parade tech)
Its important to know the vendor of this chip, as the address to
write AVI infoframes is different for those two.
This patch reads the vendor OUI signature, and
This patch adds support for YCBCR 4:4:4 CRTC output format.
To do this, this patch extends the existing YCBCR 4:2:0
framework by:
- Adding new parameter in for YCBCR 4:4:4 enum crtc_iutput_format.
- Adding case for YCBCR 4:4:4 in while setting AVI infoframes.
- Adding necessary checks in modeset
This patch adds an enum "intel_output_format" to represent
the output format of a particular CRTC. This enum will be
used to produce a RGB/YCBCR4:4:4/YCBCR4:2:0 output format
during the atomic modeset calculations.
V5:
- Created this separate patch to introduce and init output_format.
-
From: "Sharma, Shashank"
As LSPCON is a DP branch device, LSPCON vendors define
specific methods to pass AVI infoframes to the the chip.
This patch adds:
- a generic wrapper function for writing AVI infoframes for
all LSPCON devices.
- a vendor specific function to wrire AVI infoframes into
Currently, we are using a bool in CRTC state (state->ycbcr420),
to indicate modeset, that the output format is YCBCR 4:2:0. Now in
order to support other YCBCR formats, we will need more such flags.
This patch adds a new enum parameter for YCBCR 4:2:0 outputs, in the
CRTC output formats and then
From: "Sharma, Shashank"
As LSPCON is a DP branch device, LSPCON vendors define
specific methods to pass AVI infoframes to the the chip.
This patch adds:
- a generic wrapper function for writing AVI infoframes for
all LSPCON devices.
- a vendor specific function to wrire AVI infoframes into
== Series Details ==
Series: drm/i915: Kick waiters on resetting legacy rings (rev2)
URL : https://patchwork.freedesktop.org/series/47362/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f715468550d1 drm/i915: Kick waiters on resetting legacy rings
-:18:
On Tue, Aug 07, 2018 at 04:13:53PM +0100, Tvrtko Ursulin wrote:
>
> On 07/08/2018 14:21, Daniel Vetter wrote:
> > On Wed, Jul 18, 2018 at 03:24:26PM +0200, Christian König wrote:
> > > Hi Daniel,
> > >
> > > Am 18.07.2018 um 14:07 schrieb Patchwork:
> > > > == Series Details ==
> > > >
> > > >
== Series Details ==
Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev12)
URL : https://patchwork.freedesktop.org/series/36068/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4664 -> Patchwork_9935 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Op 13-08-18 om 20:15 schreef Pandiyan, Dhinakaran:
> On Mon, 2018-08-13 at 09:47 -0700, Rodrigo Vivi wrote:
>> On Mon, Aug 13, 2018 at 03:47:20PM +0200, Maarten Lankhorst wrote:
>>> Op 11-08-18 om 02:50 schreef Dhinakaran Pandiyan:
We print the last attempted entry and last exit timestamps
On Tue, Aug 14, 2018 at 02:54:31PM +0800, Feng Tang wrote:
> Hi Jani, Daniel
>
> Could you help to comment? thanks,
>
> - Feng
>
> On Thu, Jul 12, 2018 at 03:51:34PM +0800, Feng Tang wrote:
> > Hi Daniel,
> >
> > On Thu, Jul 12, 2018 at 08:54:34AM +0200, Daniel Vetter wrote:
> > > On Thu, Jul
On 10/08/18 04:01, Chris Wilson wrote:
This exercises a special case that may be of interest, waiting for a
context that may be preempted in order to reduce the wait.
Signed-off-by: Chris Wilson
---
tests/gem_sync.c | 146 +++
1 file changed,
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Clear STOP_RING bit
before restoring the context
URL : https://patchwork.freedesktop.org/series/48195/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4666_full -> Patchwork_9942_full =
== Summary -
Pushed to drm-misc-next with the whitespace fix.
Thanks for the patch.
Regards
Manasi
On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field
== Series Details ==
Series: Icelake DMC v1.07
URL : https://patchwork.freedesktop.org/series/48218/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4668 -> Patchwork_9946 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Mon, Jul 23, 2018 at 02:27:34PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> This bit was added to DP Training Aux RD interval with DP 1.3. Via
> descriptiion of the spec this field indicates the panels true
> capabilities are described in DPCD address space 02200h through
== Series Details ==
Series: drm/i915: Clear stop-engine for a pardoned reset
URL : https://patchwork.freedesktop.org/series/48202/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4666_full -> Patchwork_9943_full =
== Summary - WARNING ==
Minor unknown changes coming with
On 14/08/18 15:40, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Updated series after continuing Lionel's work.
Userspace for the feature is the media-driver project on GitHub. Please see
https://github.com/intel/media-driver/pull/271/commits.
Headline changes:
1.
No more master
== Series Details ==
Series: drm/i915/execlists: Refind the active request before resetting
URL : https://patchwork.freedesktop.org/series/48190/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4666 -> Patchwork_9939 =
== Summary - SUCCESS ==
No regressions found.
Hey Tvrtko,
Thanks for taking over this series.
I've been talking to developers using the i915/perf interface and from
their point of view, they expect the system to be in a stable
configuration when doing measurements.
One issue with this patch on Gen11 is that it will lock the system in a
Chris, for this one please let me know if it is okay to give you
authorship and to add your S-o-B.
Tvrtko
On 14/08/2018 15:40, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Global barrier is a facility to allow serialization between different
timelines.
After calling
Quoting Tvrtko Ursulin (2018-08-14 15:40:58)
> From: Chris Wilson
>
> We want to allow userspace to reconfigure the subslice configuration for
> its own use case. To do so, we expose a context parameter to allow
> adjustment of the RPCS register stored within the context image (and
> currently
From: Tvrtko Ursulin
A new workload command ('P') is added which enables per context dynamic
priority control.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 48 +-
benchmarks/wsim/README | 18
2 files changed, 65
From: Tvrtko Ursulin
Allow workloads to specify frequency of preemption points per context.
New workload command ('X') is added to allow this.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 84 --
benchmarks/wsim/README | 18 -
2
From: Tvrtko Ursulin
Notice in more places if we are running behind.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 52 ++-
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index
From: Tvrtko Ursulin
Need namespace for new commands and I never documented they are case
insensitive so it is fine.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/benchmarks/gem_wsim.c
From: Tvrtko Ursulin
Need to check we actually are in VCS2 remapping mode!
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index fd268b3ab456..850c8972f6eb 100644
---
From: Tvrtko Ursulin
MI_NOOP cannot be preempted which means up to now gem_wsim workloads were
preemptable on batch buffer granularity only.
Add MI_ARB_CHK every 100us so the new default is mid-batch preemption.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 20
From: Tvrtko Ursulin
A bag of new features and a couple fixes which came to be as I was testing
the dynamic SSEU story.
Tvrtko Ursulin (7):
gem_wsim: Check sleep times
gem_wsim: Make workload commands case sensitive
gem_wsim: Context priority support
gem_wsim: Stop keeping batches
From: Tvrtko Ursulin
The reason, which I assume was there at some point, to keep the batches
persistently memory mapped does not appear to be there. So unmap them
after creation and remove the unused structure members.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 5 +
1 file
Quoting Tvrtko Ursulin (2018-08-14 16:05:13)
> From: Tvrtko Ursulin
>
> Notice in more places if we are running behind.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> benchmarks/gem_wsim.c | 52 ++-
> 1 file changed, 46 insertions(+), 6 deletions(-)
>
>
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Clear STOP_RING bit
before restoring the context
URL : https://patchwork.freedesktop.org/series/48191/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4666 -> Patchwork_9940 =
== Summary - FAILURE
On 14/08/18 15:59, Chris Wilson wrote:
And I'd still recommend not using indirect access if we can apply the
changes immediately.
-Chris
Hangs on Gen9 :(
-
Lionel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
Quoting Tvrtko Ursulin (2018-08-14 16:05:16)
> From: Tvrtko Ursulin
>
> The reason, which I assume was there at some point, to keep the batches
> persistently memory mapped does not appear to be there. So unmap them
> after creation and remove the unused structure members.
>
> Signed-off-by:
== Series Details ==
Series: Per context dynamic (sub)slice power-gating
URL : https://patchwork.freedesktop.org/series/48194/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6a364f5371a6 drm/i915: Program RPCS for Broadwell
f2e29d92ffdf drm/i915: Record the sseu configuration
On 14/08/2018 16:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-08-14 16:05:16)
From: Tvrtko Ursulin
The reason, which I assume was there at some point, to keep the batches
persistently memory mapped does not appear to be there. So unmap them
after creation and remove the unused
== Series Details ==
Series: Per context dynamic (sub)slice power-gating
URL : https://patchwork.freedesktop.org/series/48194/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Program RPCS for Broadwell
Okay!
Commit: drm/i915: Record the sseu configuration
== Series Details ==
Series: drm/i915: Kick waiters on resetting legacy rings (rev2)
URL : https://patchwork.freedesktop.org/series/47362/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4664_full -> Patchwork_9936_full =
== Summary - SUCCESS ==
No regressions found.
100 ms is not enough time for the LSPCON adapter on Intel NUC devices to
settle. This causes dropped display modes at driver initialisation.
Increase timeout to 1000 ms.
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1570392
Signed-off-by: Fredrik Schön
---
When resetting the context image after a GPU reset, it is vital that we
do inspect the context image that was active at the time of the hang.
Even a 'pardoned' context may still have some residual corruption (e.g.
the STOP_RING bit) from issuing the GPU reset that we need to fixup
before
On Fri, Aug 10, 2018 at 08:01:16AM +0100, Chris Wilson wrote:
> It doesn't work right now and desperately needs to be fixed...
>
> Signed-off-by: Chris Wilson
On both patches:
Reviewed-by: Imre Deak
> ---
> tests/intel-ci/fast-feedback.testlist | 1 +
> tests/pm_rpm.c
Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
engine. However, sometimes we observe that upon restart, the engine
freezes again with the STOP_RING bit still asserted. By inspection, we
know that the register itself is cleared by the GPU reset, so that bit
must be preserved
When resetting the context image after a GPU reset, it is vital that we
do inspect the context image that was active at the time of the hang.
Even a 'pardoned' context may still have some residual corruption (e.g.
the STOP_RING bit) from issuing the GPU reset that we need to fixup
before
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration
From: Lionel Landwerlin
We don't need any special treatment on error so just return as soon as
possible.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
From: Tvrtko Ursulin
Updated series after continuing Lionel's work.
Userspace for the feature is the media-driver project on GitHub. Please see
https://github.com/intel/media-driver/pull/271/commits.
Headline changes:
1.
No more master allow/disallow sysfs switch. Feature is
From: Chris Wilson
We want to allow userspace to reconfigure the subslice configuration for
its own use case. To do so, we expose a context parameter to allow
adjustment of the RPCS register stored within the context image (and
currently not accessible via LRI). If the context is adjusted before
From: Tvrtko Ursulin
So far we have been relying on vm->file pointer being NULL to declare
something GGTT.
This has the unfortunate consequence that the default kernel context is
also declared GGTT and interferes with the following patch which wants to
instantiate VMA's and execute requests
From: Lionel Landwerlin
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context.
From: Tvrtko Ursulin
Global barrier is a facility to allow serialization between different
timelines.
After calling i915_gem_set_global_barrier on a request, all following
submissions on any engine will be set up as depending on this global
barrier. Once the global barrier has been completed it
From: Lionel Landwerlin
Abstract the context image access a bit.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 34 +++-
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git
When resetting the context image after a GPU reset, it is vital that we
do inspect the context image that was active at the time of the hang.
Even a 'pardoned' context may still have some residual corruption (e.g.
the STOP_RING bit) from issuing the GPU reset that we need to fixup
before
Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
engine. However, sometimes we observe that upon restart, the engine
freezes again with the STOP_RING bit still asserted. By inspection, we
know that the register itself is cleared by the GPU reset, so that bit
must be preserved
Chris Wilson writes:
> Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
> engine. However, sometimes we observe that upon restart, the engine
> freezes again with the STOP_RING bit still asserted. By inspection, we
> know that the register itself is cleared by the GPU
Quoting Chris Wilson (2018-08-14 14:11:50)
> Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
> engine. However, sometimes we observe that upon restart, the engine
> freezes again with the STOP_RING bit still asserted. By inspection, we
> know that the register itself is
== Series Details ==
Series: drm/i915/execlists: Clear STOP_RING bit before restoring the context
URL : https://patchwork.freedesktop.org/series/48187/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4665 -> Patchwork_9938 =
== Summary - SUCCESS ==
No regressions found.
Quoting Mika Kuoppala (2018-08-14 14:42:41)
> Chris Wilson writes:
>
> > Before a reset, we set the STOP_RING bit of RING_MI_MODE to freeze the
> > engine. However, sometimes we observe that upon restart, the engine
> > freezes again with the STOP_RING bit still asserted. By inspection, we
> >
On Fri, Aug 10, 2018 at 08:01:15AM +0100, Chris Wilson wrote:
> Check that we restore runtime pm around debug suspends and hibernates.
>
> v2: Differentiate between external test setup failure and one of
> interest
>
> Signed-off-by: Chris Wilson
> ---
> tests/pm_rpm.c | 18 ++
Quoting Imre Deak (2018-08-14 14:52:16)
> On Fri, Aug 10, 2018 at 08:01:15AM +0100, Chris Wilson wrote:
> > Check that we restore runtime pm around debug suspends and hibernates.
> >
> > v2: Differentiate between external test setup failure and one of
> > interest
> >
> > Signed-off-by: Chris
== Series Details ==
Series: drm/i915: set DP Main Stream Attribute for color range on DDI platforms
URL : https://patchwork.freedesktop.org/series/48145/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1c8e245b1a71 drm/i915: set DP Main Stream Attribute for color range on DDI
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