== Series Details ==
Series: drm/i915: Introduce BITS_PER_TYPE (rev2)
URL : https://patchwork.freedesktop.org/series/46055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4879 -> Patchwork_10282 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Ville Syrjälä writes:
> On Tue, Sep 25, 2018 at 04:38:03PM +0300, Mika Kuoppala wrote:
>> Using fbc with VT-d flickers also on kbl and cfl.
>>
>> Cc: Paulo Zanoni
>> Cc: Ville Syrjälä
>> Cc: Chris Wilson
>> Cc: Rodrigo Vivi
>> Cc: # v4.9+
>> Signed-off-by: Mika Kuoppala
>> ---
>>
Quoting Jani Nikula (2018-09-26 14:34:12)
> Having two separate if ladders gets increasingly hard to maintain. Put
> them together.
>
> v2: Rebase
>
> Reviewed-by: Chris Wilson # v1
Didn't spot anything wrong in the revisions, so keep the r-b on both
patches.
-Chris
== Series Details ==
Series: drm/i915: Trim partial view sg lists
URL : https://patchwork.freedesktop.org/series/50177/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4878_full -> Patchwork_10281_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues
== Series Details ==
Series: drm/i915: Introduce BITS_PER_TYPE (rev2)
URL : https://patchwork.freedesktop.org/series/46055/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
589510c0b758 drm/i915: Introduce BITS_PER_TYPE
-:30: WARNING:AVOID_BUG: Avoid crashing the kernel - try
Quoting Chris Wilson (2018-09-26 16:09:09)
> Remove gem.has_ppgtt as the information is no longer used.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
Intel-gfx mailing list
Quoting Chris Wilson (2018-09-26 16:09:08)
> Remove gem.has_ppgtt as the information is no longer used.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
Intel-gfx mailing list
== Series Details ==
Series: drm/i915: Avoid compiler warning for maybe unused gu_misc_iir
URL : https://patchwork.freedesktop.org/series/50192/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4879 -> Patchwork_10283 =
== Summary - SUCCESS ==
No regressions found.
Quoting Mika Kuoppala (2018-09-26 12:06:41)
> Chris Wilson writes:
>
> > /kisskb/src/drivers/gpu/drm/i915/i915_irq.c: warning: 'gu_misc_iir' may be
> > used uninitialized in this function [-Wuninitialized]: => 3120:10
> >
> > Silence the compiler warning by ensuring that the local variable is
Remove gem.has_ppgtt as the information is no longer used.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
tests/perf.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/tests/perf.c b/tests/perf.c
index 25a6bf191..16c1adb0e 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1547,7
Remove gem.has_ppgtt as the information is no longer used.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
tests/pm_sseu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c
index 1274e1fa6..5fdcbef22 100644
--- a/tests/pm_sseu.c
+++ b/tests/pm_sseu.c
On Wed, 26 Sep 2018, Chris Wilson wrote:
> Borrow the idea from net_dim.h to simplify the common determination of
> how many bits in a particular type (sizeof(type) * BITS_PER_BYTE).
I guess the commit message was written before you added BITS_PER_TYPE to
bitops.h. With that updated,
Sure. Acked-by: Zhi Wang
Meanwhile, I could send a patch to remove
gen8_preallocate_top_level_pdp() in i915_gem_gtt.c, which is only used
by vGPU with 32bit PPGTT (no one is going to use them after this patch
is landed)
Thanks,
Zhi.
On 09/26/18 04:02, Joonas Lahtinen wrote:
Quoting He,
Having two separate if ladders gets increasingly hard to maintain. Put
them together.
v2: Rebase
Reviewed-by: Chris Wilson # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 59
2 files
With i915.dmc_firmware_path="" it's obvious the intention is to disable
CSR firmware loading. Bypass the firmware request altogether in this
case, with more obvious debug logging.
v2: Use DRM_INFO for logging (Chris)
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
Move max firmware size to the same if ladder with firmware name and
required version. This allows us to detect the missing max size for a
platform without actually loading the firmware, and makes the whole
thing easier to maintain.
We need to move the power get earlier to allow for early return
On Wed, 26 Sep 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-09-26 14:34:12)
>> Having two separate if ladders gets increasingly hard to maintain. Put
>> them together.
>>
>> v2: Rebase
>>
>> Reviewed-by: Chris Wilson # v1
>
> Didn't spot anything wrong in the revisions, so keep the
/kisskb/src/drivers/gpu/drm/i915/i915_irq.c: warning: 'gu_misc_iir' may be used
uninitialized in this function [-Wuninitialized]: => 3120:10
Silence the compiler warning by ensuring that the local variable is
initialised and removing the guard that is confusing the older gcc.
Reported-by:
From: Tvrtko Ursulin
We mix hexa- and decimal which is confusing when reading the logs. So make
the single odd one out instance decimal for consistency.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
Later we can consider whether we should move them all to unsigned, or hex,
etc..
---
== Series Details ==
Series: drm/i915: Log HWS seqno consistently
URL : https://patchwork.freedesktop.org/series/50193/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4879 -> Patchwork_10284 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10284
Hi,
On 18/07/18 13:17, Ville Syrjälä wrote:
> On Tue, Jul 17, 2018 at 06:13:45PM +0100, Ayan Kumar Halder wrote:
>> drm_format_info table has a field 'is_yuv' to denote if the format
>> is yuv or not. The driver is expected to use this instead of
>> having a function for the same purpose.
>>
>>
On Sun, 16 Sep 2018, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> clock and data lane (in escape clocks) of DSI
> controller (DSI port 0 and 1).
> These programmed timings would be used by DSI Controller
> to calculate link transition latencies of the data and
>
== Series Details ==
Series: drm/i915: Introduce BITS_PER_TYPE (rev2)
URL : https://patchwork.freedesktop.org/series/46055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4879_full -> Patchwork_10282_full =
== Summary - WARNING ==
Minor unknown changes coming with
Quoting Jani Nikula (2018-09-26 08:06:56)
> On Tue, 25 Sep 2018, Chris Wilson wrote:
> > Quoting Jani Nikula (2018-09-25 08:18:36)
> >> On some systems we get the hotplug irq on unplug before the DDC pins
> >> have been disconnected, resulting in connector status remaining
> >> connected. Since
Borrow the idea from net_dim.h to simplify the common determination of
how many bits in a particular type (sizeof(type) * BITS_PER_BYTE).
Suggested-by: Ville Syrjälä
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
---
Chris Wilson writes:
> /kisskb/src/drivers/gpu/drm/i915/i915_irq.c: warning: 'gu_misc_iir' may be
> used uninitialized in this function [-Wuninitialized]: => 3120:10
>
> Silence the compiler warning by ensuring that the local variable is
> initialised and removing the guard that is confusing
Quoting Tvrtko Ursulin (2018-09-26 12:12:17)
> From: Tvrtko Ursulin
>
> We mix hexa- and decimal which is confusing when reading the logs. So make
> the single odd one out instance decimal for consistency.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
> Later we can consider
On Sun, 16 Sep 2018, Madhav Chauhan wrote:
> This patch defines DSI_TA_TIMING_PARAM and
> DPHY_TA_TIMING_PARAM registers used in
> dphy programming.
>
> v2: Changes (Jani N)
> - Define mask/shift for bitfields
> - Use bitfields name as per BSPEC
> - Define remaining bitfields
>
>
Quoting Joonas Lahtinen (2018-09-25 16:27:47)
> Quoting Chris Wilson (2018-09-25 14:48:20)
> > Now that we are confident in providing full-ppgtt where supported,
> > remove the ability to override the context isolation.
> >
> > v2: Remove faked aliasing-ppgtt for testing as it no longer is
On Wed, Sep 26, 2018 at 03:56:39PM +0300, Mika Kuoppala wrote:
> Ville Syrjälä writes:
>
> > On Tue, Sep 25, 2018 at 04:38:03PM +0300, Mika Kuoppala wrote:
> >> Using fbc with VT-d flickers also on kbl and cfl.
> >>
> >> Cc: Paulo Zanoni
> >> Cc: Ville Syrjälä
> >> Cc: Chris Wilson
> >> Cc:
== Series Details ==
Series: drm/i915: Avoid compiler warning for maybe unused gu_misc_iir
URL : https://patchwork.freedesktop.org/series/50192/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4879_full -> Patchwork_10283_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/50215/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/csr: keep firmware name and required
On Thu, Sep 20, 2018 at 08:49:52AM +, Kulkarni, Vandita wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Friday, September 14, 2018 9:39 PM
> > To: Kulkarni, Vandita
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> > Zanoni, Paulo R
> > Subject: Re:
== Series Details ==
Series: drm/i915: Log HWS seqno consistently (rev2)
URL : https://patchwork.freedesktop.org/series/50193/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4883 -> Patchwork_10286 =
== Summary - WARNING ==
Minor unknown changes coming with
On Wed, Sep 19, 2018 at 05:31:37PM +, Kulkarni, Vandita wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Friday, September 14, 2018 9:37 PM
> > To: Kulkarni, Vandita
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> > Zanoni, Paulo R
> > Subject: Re:
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/50215/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4882 -> Patchwork_10285 =
== Summary - SUCCESS ==
From: Tvrtko Ursulin
We mix hexa- and decimal which is confusing when reading the logs. So make
the single odd one out instance decimal for consistency.
v2:
* Do the intel_ringbuffer.c as well. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
Quoting Tvrtko Ursulin (2018-09-26 15:50:33)
> From: Tvrtko Ursulin
>
> We mix hexa- and decimal which is confusing when reading the logs. So make
> the single odd one out instance decimal for consistency.
>
> v2:
> * Do the intel_ringbuffer.c as well. (Chris Wilson)
>
> Signed-off-by: Tvrtko
Quoting Chris Wilson (2018-09-26 16:13:53)
> Nobody uses the function directly, instead using the various helpers to
> determine if ppgtt is present.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
Reviewed-by: Joonas Lahtinen
Regards, Joonas
On Mon, 2018-09-24 at 23:02 -0700, dhinakaran.pandi...@gmail.com wrote:
> On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> > For PSR2 we don't have the option to keep main link enabled while
> > PSR2 is active, so don't configure sink DPCD with a wrong value.
>
> Is this what the
On Mon, 2018-09-24 at 23:08 -0700, dhinakaran.pandi...@gmail.com wrote:
> On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> > ALPM is a requirement and we don't need to keep it's cached, what
> > were done in commit 97c9de66ca80
> > ("drm/i915/psr: Fix ALPM cap check for PSR2") but
[+cc Intel DRM maintainers, etc]
On Wed, Sep 26, 2018 at 08:14:01AM -0700, Bin Meng wrote:
> Add more PCI IDs to the Intel GPU "spurious interrupt" quirk table,
> which are known to break.
Do you have a reference for this? Any public bug reports, bugzilla,
Intel spec reference or errata?
On Wed, 2018-09-26 at 17:46 +, Souza, Jose wrote:
> On Mon, 2018-09-24 at 23:02 -0700, dhinakaran.pandi...@gmail.com
> wrote:
> > On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote:
> > > For PSR2 we don't have the option to keep main link enabled while
> > > PSR2 is active, so
Hi Shawn,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.19-rc5 next-20180926]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Josh ,
Apologies about the previous one.
Sending a new PR:
The following changes since commit 44d4fca9922a252a0bd81f6307bcc072a78da54a:
Merge https://github.com/pmachata/linux-firmware (2018-09-13 11:45:40 -0400)
are available in the git repository at:
== Series Details ==
Series: series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL : https://patchwork.freedesktop.org/series/50236/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Share PSR and PSR2 exit mask
Okay!
Commit: drm/i915/psr:
Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 34
1 file changed, 13 insertions(+), 21
ICL spec states that this bit is now reserved.
Bspec: 7722
v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title
Cc: Jani Nikula
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
This WA also works fine for PSR2, triggering a selective update when
possible.
Acked-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
v2(Dhinakaran): Using else of dev_priv->psr.psr2_enabled to set
DP_PSR_CRC_VERIFICATION
Cc:
ALPM is a requirement and we don't need to keep it's cached, what
were done in commit 97c9de66ca80
("drm/i915/psr: Fix ALPM cap check for PSR2") but the alpm was not
removed from i915_psr.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
wrong value.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 11 +++
1 file changed, 7 insertions(+), 4
We are already handling all PSR2 errors, so we can drop this TODO.
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
Quoting Ville Syrjälä (2018-09-26 10:27:40)
> On Tue, Sep 25, 2018 at 09:29:44PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-09-25 20:37:07)
> > > From: Ville Syrjälä
> > > + /* Catch potential overflows early */
> > > + if (add_overflows(mul_u32_u32(height,
Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.
v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
v3: s/USES/HAS/ to match usage and reject attempts to load the module on
old GVT-g setups that do not
== Series Details ==
Series: series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL : https://patchwork.freedesktop.org/series/50236/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4883 -> Patchwork_10287 =
== Summary - FAILURE ==
Serious unknown
Hi Shawn,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19-rc5 next-20180926]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
== Series Details ==
Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL : https://patchwork.freedesktop.org/series/50143/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Remove i915.enable_ppgtt override
+drivers/gpu/drm/i915/i915_drv.c:348:25: warning:
== Series Details ==
Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL : https://patchwork.freedesktop.org/series/50143/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4885 -> Patchwork_10288 =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: drm/i915: Log HWS seqno consistently (rev2)
URL : https://patchwork.freedesktop.org/series/50193/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4883_full -> Patchwork_10286_full =
== Summary - WARNING ==
Minor unknown changes coming with
On Tue, 2018-09-25 at 11:16 +0300, Jani Nikula wrote:
> On Mon, 24 Sep 2018, José Roberto de Souza
> wrote:
> > For ICL type-c ports there is a aux power restriction, it can only
> > be
> > enabled while there is sink connected.
> >
> > BSpec: 21750
> >
> > Cc: Maarten Lankhorst
> >
On Tue, 2018-09-25 at 15:17 +0300, Ville Syrjälä wrote:
> On Mon, Sep 24, 2018 at 06:16:49PM -0700, José Roberto de Souza
> wrote:
> > For ICL type-c ports there is a aux power restriction, it can only
> > be
> > enabled while there is sink connected.
>
> That can't be entirely true because it's
On Fri, Sep 21, 2018 at 07:39:41PM +0200, Maarten Lankhorst wrote:
> Skylake style watermarks program the UV parameters into wm->uv_wm,
> and have a separate DDB allocation for UV blocks into the same plane.
>
> Gen11 watermarks have a separate plane for Y and UV, with separate
> mechanisms. The
On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> upsampler to upscale YUV420 to YUV444 and the scaler should only be
> used for upscaling. Because of this we shouldn't program the scalers
> in planar mode if
On Tue, Sep 18, 2018 at 02:48:13PM -0700, Rodrigo Vivi wrote:
> On Tue, Sep 18, 2018 at 01:47:10PM -0700, José Roberto de Souza wrote:
> > Right now RESET_PCH_HANDSHAKE_ENABLE is enabled all the times inside
> > of intel_power_domains_init_hw() and if PCH is NOP it is unsed in
> >
On Wed, 26 Sep 2018 16:44:16 -0700
Guang Bai wrote:
> On Tue, 25 Sep 2018 10:18:36 +0300
> Jani Nikula wrote:
>
> > On some systems we get the hotplug irq on unplug before the DDC pins
> > have been disconnected, resulting in connector status remaining
> > connected. Since previous attempts at
This new AML PCI ID uses the same gen graphics as Coffe Lake not a
Kaby Lake one like the other AMLs.
So to make it more explicit renaming INTEL_AML_GT2_IDS to
INTEL_AML_KBL_GT2_IDS and naming this id as INTEL_AML_CFL_GT2_IDS.
v2:
- missed add new AML macro to INTEL_CFL_IDS()
- added derivated
== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/50037/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4888 -> Patchwork_10289 =
== Summary - FAILURE ==
Serious unknown changes coming with
On Tue, 25 Sep 2018 10:18:36 +0300
Jani Nikula wrote:
> On some systems we get the hotplug irq on unplug before the DDC pins
> have been disconnected, resulting in connector status remaining
> connected. Since previous attempts at using hotplug live status before
> DDC have failed, the only
== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID (rev2)
URL : https://patchwork.freedesktop.org/series/50037/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b83389a0d094 drm/i915/aml: Add new Amber Lake PCI ID
-:52: ERROR:COMPLEX_MACRO: Macros with complex
On Wed, Sep 26, 2018 at 11:47:07AM +0100, Chris Wilson wrote:
> Borrow the idea from net_dim.h to simplify the common determination of
> how many bits in a particular type (sizeof(type) * BITS_PER_BYTE).
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc:
== Series Details ==
Series: drm/i915: Avoid compiler warning for maybe unused gu_misc_iir
URL : https://patchwork.freedesktop.org/series/50192/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b7c8e42bbb5e drm/i915: Avoid compiler warning for maybe unused gu_misc_iir
-:6:
> -Original Message-
> From: Nikula, Jani
> Sent: Wednesday, September 26, 2018 6:29 PM
> To: Chauhan, Madhav ; intel-
> g...@lists.freedesktop.org
> Cc: Kulkarni, Vandita ; Vivi, Rodrigo
> ; Rangappa, Komala B
> ; Chauhan, Madhav
>
> Subject: Re: [PATCH v6 06/20] drm/i915/icl: Program
Nobody uses the function directly, instead using the various helpers to
determine if ppgtt is present.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
lib/ioctl_wrappers.c | 5 ++---
lib/ioctl_wrappers.h | 1 -
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git
Commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link quality check,
unconditionally during long pulse"")' applies a work around for sinks
that don't signal link loss. The work around does not need to have to be
that broad as the issue was seen with only one particular monitor; limit
this only
Comment claims link needs to be retrained because the connected sink raised
a long pulse to indicate link loss. If the sink did so,
intel_dp_hotplug() would have handled link retraining. Looking at the
logs in Bugzilla referenced in commit '3cf71bc9904d ("drm/i915: Re-apply
Perform link quality
We have two cases of intel_dp to intel_encoder conversions, use a
local variable to store the conversion.
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
1 file changed, 3 insertions(+), 5
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/dp: Fix link retraining comment
in intel_dp_long_pulse()
URL : https://patchwork.freedesktop.org/series/50251/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5fd2877f631b drm/i915/dp: Fix link retraining
== Series Details ==
Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL : https://patchwork.freedesktop.org/series/50143/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4885_full -> Patchwork_10288_full =
== Summary - SUCCESS ==
No regressions found.
==
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Wednesday, September 26, 2018 2:41 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>dri-de...@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx]
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, September 26, 2018 3:12 PM
>To: Maarten Lankhorst
>Cc: Shankar, Uma ; Adam Jackson
>; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
Hey,
sön 2018-09-16 klockan 13:45 +0530 skrev Uma Shankar:
> This is how a typical display color hardware pipeline looks like:
> +---+
> |RAM|
> | +--++-++-+ |
> | | FB 1 || FB
On Tue, 25 Sep 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-09-25 08:18:36)
>> On some systems we get the hotplug irq on unplug before the DDC pins
>> have been disconnected, resulting in connector status remaining
>> connected. Since previous attempts at using hotplug live status before
On 25/09/2018 20:37, Ville Syrjala wrote:
From: Ville Syrjälä
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
v2: Use intel_remapped_plane_info base type
From: Tvrtko Ursulin
Partial views are small but there can be many of them, and since the sg
list space for them is allocated pessimistically, we can save some slab by
trimming the unused tail entries.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
On the other hand
Quoting He, Min (2018-09-26 04:06:25)
> No. We changed to full 48bit ppgtt long time ago. :)
So would that mean the change is OK to do?
Acked-by from you, Zhi, would be good to have for documentation purposes
in that case :)
Regards, Joonas
>
> > -Original Message-
> > From: Wang, Zhi
Quoting Tvrtko Ursulin (2018-09-26 09:03:53)
> From: Tvrtko Ursulin
>
> Partial views are small but there can be many of them, and since the sg
> list space for them is allocated pessimistically, we can save some slab by
> trimming the unused tail entries.
>
> Signed-off-by: Tvrtko Ursulin
>
On 26/09/2018 09:15, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-26 09:03:53)
From: Tvrtko Ursulin
Partial views are small but there can be many of them, and since the sg
list space for them is allocated pessimistically, we can save some slab by
trimming the unused tail entries.
Op 01-08-18 om 16:01 schreef Shankar, Uma:
>
>> -Original Message-
>> From: Adam Jackson [mailto:a...@redhat.com]
>> Sent: Wednesday, August 1, 2018 1:24 AM
>> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>> dri-de...@lists.freedesktop.org
>> Cc: Syrjala, Ville ; Lankhorst, Maarten
Op 24-07-18 om 17:45 schreef Uma Shankar:
> Based on colorspace property value create an infoframe
> with appropriate colorspace. This can be used to send an
> infoframe packet with proper colorspace value set which
> will help to enable wider color gamut like BT2020 on sink.
>
> Signed-off-by:
== Series Details ==
Series: drm/i915: Trim partial view sg lists
URL : https://patchwork.freedesktop.org/series/50177/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4878 -> Patchwork_10281 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10281 need
On Tue, Sep 25, 2018 at 08:59:03PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-25 20:37:14)
> > From: Ville Syrjälä
> >
> > With gtt remapping in place we can use arbitrarily large
> > framebuffers. Let's bump the limits to 16kx16k on gen7+.
> > The limit was chosen to match the
== Series Details ==
Series: drm/i915: Trim partial view sg lists
URL : https://patchwork.freedesktop.org/series/50177/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Trim partial view sg lists
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:16: warning:
>-Original Message-
>From: Lankhorst, Maarten
>Sent: Wednesday, September 26, 2018 1:05 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>dri-de...@lists.freedesktop.org
>Cc: Syrjala, Ville ; alexandru-
>cosmin.gheor...@arm.com; emil.l.veli...@gmail.com;
>seanp...@chromium.org;
On Tue, Sep 25, 2018 at 09:22:34PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-25 20:37:10)
> > From: Ville Syrjälä
> >
> > Extend the rotated vma mock selftest to cover remapped vmas as
> > well.
> >
> > TODO: reindent the loops I guess? Left like this for now to
> > ease
On Tue, Sep 25, 2018 at 09:29:44PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-25 20:37:07)
> > From: Ville Syrjälä
> >
> > Let's try to make sure the fb offset computations never hit
> > an integer overflow by making sure the entire fb stays
> > below 32bits. framebuffer_check()
On Tue, Sep 25, 2018 at 09:40:30PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-25 20:37:11)
> > From: Ville Syrjälä
> >
> > Add a live selftest to excercise rotated/remapped vmas. We simply
> > write through the rotated/remapped vma, and confirm that the data
> > appears in the
Quoting Tvrtko Ursulin (2018-09-26 09:30:41)
>
> On 26/09/2018 09:15, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-26 09:03:53)
> >> From: Tvrtko Ursulin
> >>
> >> Partial views are small but there can be many of them, and since the sg
> >> list space for them is allocated
On Thu, 13 Sep 2018, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 0h
On Wed, Sep 26, 2018 at 11:08:37AM +0200, Maarten Lankhorst wrote:
> Op 01-08-18 om 16:01 schreef Shankar, Uma:
> >
> >> -Original Message-
> >> From: Adam Jackson [mailto:a...@redhat.com]
> >> Sent: Wednesday, August 1, 2018 1:24 AM
> >> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
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