[Intel-gfx] [PATCH] drm/i915: Complete the fences as they are cancelled due to wedging

We inspect the requests under the assumption that they will be marked as completed when they are removed from the queue. Currently however, in the process of wedging the requests will be removed from the queue before they are completed, so rearrange the code to complete the fences before the locks

[Intel-gfx] [PATCH 3/7] drm/i915: Allocate a common scratch page

Currently we allocate a scratch page for each engine, but since we only ever write into it for post-sync operations, it is not exposed to userspace nor do we care for coherency. As we then do not care about its contents, we can use one page for all, reducing our allocations and avoid complications

[Intel-gfx] [PATCH 1/7] drm/i915: Complete the fences as they are cancelled due to wedging

We inspect the requests under the assumption that they will be marked as completed when they are removed from the queue. Currently however, in the process of wedging the requests will be removed from the queue before they are completed, so rearrange the code to complete the fences before the locks

[Intel-gfx] [PATCH 7/7] drm/i915/execlists: Apply a full mb before execution for Braswell

Braswell is really picky about having our writes posted to memory before we execute or else the GPU may see stale values. A wmb() is insufficient as it only ensures the writes are visible to other cores, we need a full mb() to ensure the writes are in memory and visible to the GPU. The most

[Intel-gfx] [PATCH 4/7] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly

If all else fails and we are stuck eternally waiting for the undying request, abandon all hope. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 2/7] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

Ensure that the sync registers are cleared every time we restart the ring to avoid stale values from creeping in from random neutrinos. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[Intel-gfx] [PATCH 5/7] drm/i915/selftests: Reorder request allocation vs vma pinning

Impose a restraint that we have all vma pinned for a request prior to its allocation. This is to simplify request construction, and should facilitate unravelling the lock interdependencies later. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--

[Intel-gfx] [PATCH 6/7] drm/i915: Pipeline PDP updates for Braswell

Currently we face a severe problem on Braswell that manifests as invalid ppGTT accesses. The code tries to maintain the PDP (page directory pointers) inside the context in two ways, direct write into the context and a pipelined LRI update. The direct write into the context is fundamentally racy as

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53348/ State : warning == Summary == $ dim checkpatch origin/drm-tip a7232ddbd965 drm/i915: Complete the fences as they

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53348/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Complete the

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915: Complete the fences as they are cancelled due to wedging (rev2)

== Series Details == Series: series starting with drm/i915: Complete the fences as they are cancelled due to wedging (rev2) URL : https://patchwork.freedesktop.org/series/53308/ State : failure == Summary == Applying: drm/i915: Complete the fences as they are cancelled due to wedging

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c

== Series Details == Series: series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c URL : https://patchwork.freedesktop.org/series/53350/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10991_full

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53348/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10990_full

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats

== Series Details == Series: series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats URL : https://patchwork.freedesktop.org/series/53352/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10992_full

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/7] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53348/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10990

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/fbdev: Make skip_vt_switch the default (rev3)

== Series Details == Series: drm/fbdev: Make skip_vt_switch the default (rev3) URL : https://patchwork.freedesktop.org/series/53094/ State : success == Summary == CI Bug Log - changes from CI_DRM_5234_full -> Patchwork_10980_full Summary

[Intel-gfx] [PATCH 4/4] drm/i915/dsi: Call drm_connector_cleanup on vlv_dsi_init error exit path

If we exit vlv_dsi_init() because we failed to find a fixed_mode, then we've already called drm_connector_init() and we should call drm_connector_cleanup() to unregister the connector object. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/vlv_dsi.c | 4 +++- 1 file changed, 3

[Intel-gfx] [PATCH 1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats

There are 3 problems with the dsi code's pipe_bpp handling for 6 bpc pixel-formats which this commit addresses: 1) It assumes that the pipe_bpp is the same as the bpp going over the dsi lanes. This assumption is not valid for MIPI_DSI_FMT_RGB666, where pipe_bpp should be 18 so that we do proper

[Intel-gfx] [PATCH 2/4] drm/i915/dsi: Move logging of DSI VBT parameters to a helper function

This is a preparation patch for moving the calling of *_dphy_param_init() out of intel_dsi_vbt_init. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 77 +++- 1 file changed, 42 insertions(+), 35 deletions(-) diff --git

[Intel-gfx] [PATCH 4/4] drm/i915/dsi: Read back pclk set by GOP and use that as pclk (v3)

The GOP sometimes initializes the pclk at a (slightly) different frequency then the pclk which we've calculated. This commit makes the DSI code read-back the pclk set by the GOP and if that is within a reasonable margin of the calculated pclk, uses that instead. This fixes the first modeset

[Intel-gfx] [PATCH 1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c

The next patch in this series uses intel_fuzzy_clock_check from the vlv_dsi.c code. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 3/4] drm/i915/dsi: Move vlv/icl_dphy_param_init call out of intel_dsi_vbt_init

The vlv/icl_dphy_param_init calls do various calculations to set dphy parameters based on the pclk. Move the calling of vlv/icl_dphy_param_init to vlv_dsi_init to give vlv_dsi_init a chance to tweak the pclk before these calculations are done. This also removes the single "if

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats

== Series Details == Series: series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats URL : https://patchwork.freedesktop.org/series/53352/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7325fa834a45 drm/i915/dsi: Fix pipe_bpp for handling for

[Intel-gfx] ✗ Fi.CI.IGT: failure for Restore workarounds after engine reset and unify their handling (rev2)

== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5235_full -> Patchwork_10981_full

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c

== Series Details == Series: series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c URL : https://patchwork.freedesktop.org/series/53350/ State : warning == Summary == $ dim checkpatch origin/drm-tip 39f8e6ecede8 drm/i915: Make

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats

== Series Details == Series: series starting with [1/4] drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats URL : https://patchwork.freedesktop.org/series/53352/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10992

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c

== Series Details == Series: series starting with [1/4] drm/i915: Make intel_fuzzy_clock_check available outside of intel_display.c URL : https://patchwork.freedesktop.org/series/53350/ State : success == Summary == CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10991

[Intel-gfx] [PATCH 2/4] drm/i915/dsi: Enable dithering for 6 bpc panels

The display engine has 2 dithering enable bits which both need to be set for dithering to happen, 1 in the PIPECONF register which is taken care of by i9xx_set_pipeconf() and a second bit at the encoder level. The dsi code was not setting the encoder level dithering enable bit causing dithering

[Intel-gfx] [PATCH 3/4] drm/i915/dsi: Adjust crtc_clock for burst_mode_ratio

On devices with a burst_mode_ratio which is not 100 (1:1), the pclk will have a different value then drm_display_mode.clock . On a Prowise PT301 tablet where vbt.lfp_lvds_vbt_mode.clock is 66100 and burst_mode_ratio is 130 this leads to the following errors: [drm:pipe_config_err [i915]] *ERROR*

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

== Series Details == Series: series starting with [CI,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define URL : https://patchwork.freedesktop.org/series/53337/ State : success == Summary == CI Bug Log - changes from CI_DRM_5236_full -> Patchwork_10983_full

Re: [Intel-gfx] [PATCH 7/7] drm/i915/execlists: Apply a full mb before execution for Braswell

Quoting Chris Wilson (2018-12-01 09:52:31) > Braswell is really picky about having our writes posted to memory before > we execute or else the GPU may see stale values. A wmb() is insufficient > as it only ensures the writes are visible to other cores, we need a full > mb() to ensure the writes

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it

== Series Details == Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it URL : https://patchwork.freedesktop.org/series/53341/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10985_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/dp/fec: Fix static check warning

== Series Details == Series: i915/dp/fec: Fix static check warning URL : https://patchwork.freedesktop.org/series/53342/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10986_full Summary ---

Re: [Intel-gfx] [PATCH] i915/dp/fec: Fix static check warning

Quoting Anusha (2018-11-30 23:14:28) > From: Anusha Srivatsa > > Fix indentation error in the commit: > commit 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register") > > Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register") > Reported-by: Dan Carpenter > Cc:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)

== Series Details == Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev2) URL : https://patchwork.freedesktop.org/series/53340/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10987_full