[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest

== Series Details == Series: series starting with [1/2] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest URL : https://patchwork.freedesktop.org/series/65450/ State : success == Summary == CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14092

[Intel-gfx] [PATCH v6 1/3] drm/i915: enum transcoder and pipe are moved into i915_drm.h

For the reusability of the enum transcoder and enum pipe in other driver modules (like mei_hdcp), enum port definition is moved from I915 local header intel_display.h to drm/i915_drm.h Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/display/intel_display.h | 44 ---

[Intel-gfx] [PATCH v6 0/3] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+

Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement from DDI into transcoder. v6: Extending the I915-MEI HDCP interface to include the transcoder. For register programming, transcoder is used instead of PIPE. Just readability improvement pipe and transcoder

[Intel-gfx] [PATCH v6 3/3] drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+

From Gen12 onwards, HDCP HW block is implemented within transcoders. Till Gen11 HDCP HW block was part of DDI. Hence required changes in HW programming is handled here. As ME FW needs the transcoder detail on which HDCP is enabled on Gen12+ platform, we are populating the detail in

[Intel-gfx] [PATCH v6 2/3] misc/mei_hdcp: Adding the transcoder detail in payload input

ME FW takes the transcoder details for Gen12+ platforms, as HDCP HW block is moved to transcoders. hdcp_port_data is extended with enum transcoder. Payload structure is modified and populated from the hdcp_port_data. Signed-off-by: Ramalingam C --- drivers/misc/mei/hdcp/mei_hdcp.c | 27

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4)

== Series Details == Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4) URL : https://patchwork.freedesktop.org/series/63432/ State : warning == Summary == $ dim checkpatch origin/drm-tip a1edb75d36db drm/i915: enum transcoder and pipe are moved into i915_drm.h 4dade0c7f121

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Switch obj->mm.lock lockdep annotations on its head

Quoting Daniel Vetter (2019-08-20 09:19:49) > +#include > + > #include "display/intel_frontbuffer.h" > #include "gt/intel_gt.h" > #include "i915_drv.h" > @@ -51,6 +53,15 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, > { > mutex_init(>mm.lock); > > + if

[Intel-gfx] [CI] drm/i915: Be defensive when starting vma activity

Before we acquire the vma for GPU activity, ensure that the underlying object is not already in the process of being freed. Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_vma.c | 3 +-- drivers/gpu/drm/i915/i915_vma.h | 8 2 files changed, 9

[Intel-gfx] [CI] drm/i915/tgl: Gen12 csb support

From: Daniele Ceraolo Spurio The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the

Re: [Intel-gfx] [PATCH v6 2/3] misc/mei_hdcp: Adding the transcoder detail in payload input

On 2019-08-20 at 14:15:47 +0530, Winkler, Tomas wrote: > > > > > ME FW takes the transcoder details for Gen12+ platforms, as HDCP HW block is > > moved to transcoders. > > > > hdcp_port_data is extended with enum transcoder. Payload structure is > > modified and populated from the

[Intel-gfx] [CI] drm/i915/tgl: Gen12 csb support

From: Daniele Ceraolo Spurio The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev3)

== Series Details == Series: Tiger Lake batch 3 (rev3) URL : https://patchwork.freedesktop.org/series/65290/ State : warning == Summary == $ dim checkpatch origin/drm-tip 58746e12b1f7 drm/i915/tgl: disable DDIC 372e74bfab57 drm/i915/tgl: add support for reading the timestamp frequency

Re: [Intel-gfx] [PATCH v2 32/40] drm/i915/tgl: Updated Private PAT programming

Quoting Lucas De Marchi (2019-08-17 10:38:54) > From: Michel Thierry > > Gen12 removes the target-cache and age fields from the private PAT > because MOCS now have the capability to set these itself. Only memory-type > field should be programmed in the ppat, the reminded bits are reserved. > >

Re: [Intel-gfx] [PATCH v2 26/40] HACK: drm/i915/tgl: Gen12 render context size

Quoting Lucas De Marchi (2019-08-17 10:38:48) > From: Daniele Ceraolo Spurio > > Re-use Gen11 context size for now. > > [ Lucas: add HACK since this is a temporary patch that needs to be > confirmed: we need to check BSpec 46255 and recompute ] We can drop the HACK and just refer to this as

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3 (rev3)

== Series Details == Series: Tiger Lake batch 3 (rev3) URL : https://patchwork.freedesktop.org/series/65290/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: disable DDIC Okay! Commit: drm/i915/tgl: add support for reading the timestamp

[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65437/ State : success == Summary == CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full Summary ---

Re: [Intel-gfx] [PATCH 3/9] drm/i915: Add subslice stride runtime parameter

Quoting Stuart Summers (2019-08-19 22:49:57) > Add a new parameter, ss_stride, to the runtime info > structure. This is used to mirror the userspace concept > of subslice stride, which is a range of subslices per slice. > > This patch simply adds the definition and updates usage > in the

Re: [Intel-gfx] [PATCH 4/9] drm/i915: Add EU stride runtime parameter

Quoting Stuart Summers (2019-08-19 22:49:58) > Add a new SSEU runtime parameter, eu_stride, which is > used to mirror the userspace concept of a range of EUs > per subslice. > > This patch simply adds the parameter and updates usage > in the QUERY_TOPOLOGY_INFO handler. > > Signed-off-by: Stuart

Re: [Intel-gfx] [PATCH 5/9] drm/i915: Add function to set subslices

Quoting Stuart Summers (2019-08-19 22:49:59) > Add a new function to set a range of subslices for a > specified slice based on a given mask. > > v2: Use local variable for subslice_mask on HSW and > clean up a few other subslice_mask local variable > changes > > Signed-off-by: Stuart

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice

Quoting Stuart Summers (2019-08-19 22:50:00) > Add a new function to determine whether a particular slice > has a given subslice. > > Signed-off-by: Stuart Summers > --- > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++ > drivers/gpu/drm/i915/intel_device_info.c | 9 - > 2

Re: [Intel-gfx] [PATCH] drm/kms: Catch mode_object lifetime errors

On Tue, 20 Aug 2019, Daniel Vetter wrote: > On Sat, Aug 17, 2019 at 12:42 AM Souza, Jose wrote: >> On Sat, 2019-06-29 at 17:39 +0200, Daniel Vetter wrote: >> > On Fri, Jun 28, 2019 at 7:24 PM Sean Paul wrote: >> > > On Fri, Jun 14, 2019 at 08:17:23AM +0200, Daniel Vetter wrote: >> > > > Only

Re: [Intel-gfx] [PATCH] drm/kms: Catch mode_object lifetime errors

On Tue, Aug 20, 2019 at 11:28 AM Jani Nikula wrote: > > On Tue, 20 Aug 2019, Daniel Vetter wrote: > > On Sat, Aug 17, 2019 at 12:42 AM Souza, Jose wrote: > >> On Sat, 2019-06-29 at 17:39 +0200, Daniel Vetter wrote: > >> > On Fri, Jun 28, 2019 at 7:24 PM Sean Paul wrote: > >> > > On Fri, Jun

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Assume exclusive access to objects inside resume

== Series Details == Series: drm/i915: Assume exclusive access to objects inside resume URL : https://patchwork.freedesktop.org/series/65434/ State : success == Summary == CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14087_full

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Add function to set SSEU info per platform

Stuart Summers writes: > Add a new function to allow each platform to set maximum > slice, subslice, and EU information to reduce code duplication. > > Signed-off-by: Stuart Summers Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_sseu.c | 8 + >

Re: [Intel-gfx] [PATCH] drm/kms: Catch mode_object lifetime errors

On Sat, Aug 17, 2019 at 12:42 AM Souza, Jose wrote: > On Sat, 2019-06-29 at 17:39 +0200, Daniel Vetter wrote: > > On Fri, Jun 28, 2019 at 7:24 PM Sean Paul wrote: > > > On Fri, Jun 14, 2019 at 08:17:23AM +0200, Daniel Vetter wrote: > > > > Only dynamic mode objects, i.e. those which are

[Intel-gfx] [PATCH] drm/i915: Serialize insertion into the file->mm.request_list

Currently, we remove the from per-file request list for throttling and retirement under a dedicated spinlock, but insertion is governed by struct_mutex. This needs to be the same lock so that the retirement/insertion of neighbouring requests (at the tail) doesn't break the list. Signed-off-by:

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915: enum transcoder and pipe are moved into i915_drm.h

> > For the reusability of the enum transcoder and enum pipe in other driver > modules (like mei_hdcp), enum port definition is moved from I915 local header > intel_display.h to drm/i915_drm.h Don't you need to name space those definitions in the global space, I guess there are a lot of

Re: [Intel-gfx] [PATCH 2/5] kernel.h: Add non_block_start/end()

On Fri 16-08-19 11:31:45, Jason Gunthorpe wrote: > On Fri, Aug 16, 2019 at 02:26:25PM +0200, Michal Hocko wrote: [...] > > I believe I have given some examples when introducing __GFP_NOLOCKDEP. > > Okay, I think that is 7e7844226f10 ("lockdep: allow to disable reclaim > lockup detection") Hmm,

[Intel-gfx] [PATCH 3/4] kernel.h: Add non_block_start/end()

In some special cases we must not block, but there's not a spinlock, preempt-off, irqs-off or similar critical section already that arms the might_sleep() debug checks. Add a non_block_start/end() pair to annotate these. This will be used in the oom paths of mmu-notifiers, where blocking is not

[Intel-gfx] [PATCH 3/3] drm/i915: use might_lock_nested in get_pages annotation

So strictly speaking the existing annotation is also ok, because we have a chain of obj->mm.lock#I915_MM_GET_PAGES -> fs_reclaim -> obj->mm.lock (the shrinker cannot get at an object while we're in get_pages, hence this is safe). But it's confusing, so try to take the right subclass of the lock.

[PATCH 1/3] drm/i915: Switch obj->mm.lock lockdep annotations on its head

The trouble with having a plain nesting flag for locks which do not naturally nest (unlike block devices and their partitions, which is the original motivation for nesting levels) is that lockdep will never spot a true deadlock if you screw up. This patch is an attempt at trying better, by

[PATCH 2/3] lockdep: add might_lock_nested()

Necessary to annotate functions where we might acquire a mutex_lock_nested() or similar. Needed by i915. Signed-off-by: Daniel Vetter Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Will Deacon Cc: linux-ker...@vger.kernel.org --- include/linux/lockdep.h | 8 1 file changed, 8 insertions(+)

[Intel-gfx] [PATCH 0/4] mmu notifier debug annotations/checks

Hi all, Here's the respin. Changes: - 2 patches for checking return values of callbacks dropped, they landed - move the lockdep annotations ahead, since I think that part is less contentious. lockdep map now also annotates invalidate_range_end, as requested by Jason. - add a patch to prime

[Intel-gfx] [PATCH 4/4] mm, notifier: Catch sleeping/blocking for !blockable

We need to make sure implementations don't cheat and don't have a possible schedule/blocking point deeply burried where review can't catch it. I'm not sure whether this is the best way to make sure all the might_sleep() callsites trigger, and it's a bit ugly in the code flow. But it gets the job

[Intel-gfx] [PATCH 2/4] mm, notifier: Prime lockdep

We want to teach lockdep that mmu notifiers can be called from direct reclaim paths, since on many CI systems load might never reach that level (e.g. when just running fuzzer or small functional tests). Motivated by a discussion with Jason. I've put the annotation into mmu_notifier_register

[Intel-gfx] [PATCH 1/4] mm, notifier: Add a lockdep map for invalidate_range_start/end

This is a similar idea to the fs_reclaim fake lockdep lock. It's fairly easy to provoke a specific notifier to be run on a specific range: Just prep it, and then munmap() it. A bit harder, but still doable, is to provoke the mmu notifiers for all the various callchains that might lead to them.

Re: [Intel-gfx] [PATCH] drm/i915: Serialize insertion into the file->mm.request_list

On Tue, 20 Aug 2019 at 09:26, Chris Wilson wrote: > > Currently, we remove the from per-file request list for throttling and > retirement under a dedicated spinlock, but insertion is governed by > struct_mutex. This needs to be the same lock so that the > retirement/insertion of neighbouring

Re: [Intel-gfx] [PATCH v6 2/3] misc/mei_hdcp: Adding the transcoder detail in payload input

> > ME FW takes the transcoder details for Gen12+ platforms, as HDCP HW block is > moved to transcoders. > > hdcp_port_data is extended with enum transcoder. Payload structure is > modified and populated from the hdcp_port_data. > > Signed-off-by: Ramalingam C > --- >

Re: [Intel-gfx] [PATCH v6 1/3] drm/i915: enum transcoder and pipe are moved into i915_drm.h

On 2019-08-20 at 14:14:03 +0530, Winkler, Tomas wrote: > > > > > > For the reusability of the enum transcoder and enum pipe in other driver > > modules (like mei_hdcp), enum port definition is moved from I915 local > > header > > intel_display.h to drm/i915_drm.h > > Don't you need to name

[Intel-gfx] [PATCH] drm/i915/tgl: Lower cdclk for sub 4k resolutions

In order to achieve improved power savings we can tune down CD clock frequency for sub 4k resolutions. The maximum CD clock frequency for sub 4k resolutions is set to 172.8 MHz. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cdclk.c | 26 +-

[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65437/ State : success == Summary == CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full Summary ---

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Dynamically allocate s0ix struct for VLV

Quoting Daniele Ceraolo Spurio (2019-08-20 03:01:46) > This is only required for a single platform so no need to reserve the > memory on all of them. > > This removes the last direct dependency of i915_drv.h on i915_reg.h > (apart from the i915_reg_t definition). > > v2: drop unneeded diff, keep

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mmu notifier debug annotations/checks

== Series Details == Series: mmu notifier debug annotations/checks URL : https://patchwork.freedesktop.org/series/65465/ State : warning == Summary == $ dim checkpatch origin/drm-tip e625d02db27d mm, notifier: Add a lockdep map for invalidate_range_start/end -:129: WARNING:NO_AUTHOR_SIGN_OFF:

[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65435/ State : success == Summary == CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14088_full Summary ---

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Introduce intel_reg_types.h

Quoting Daniele Ceraolo Spurio (2019-08-20 03:01:47) > With the introduction of display uncore, we want to categorize registers > between display and non-display. To help us getting it right, it will > be useful to move the display registers to a new file that can be used > without including

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Switch obj->mm.lock lockdep annotations on its head

== Series Details == Series: series starting with [1/3] drm/i915: Switch obj->mm.lock lockdep annotations on its head URL : https://patchwork.freedesktop.org/series/65467/ State : warning == Summary == $ dim checkpatch origin/drm-tip ed358b6f33d9 drm/i915: Switch obj->mm.lock lockdep

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4)

== Series Details == Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev4) URL : https://patchwork.freedesktop.org/series/63432/ State : success == Summary == CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14093 Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for dmabuf: Mark up onstack timer for selftests

== Series Details == Series: dmabuf: Mark up onstack timer for selftests URL : https://patchwork.freedesktop.org/series/65477/ State : failure == Summary == Applying: dmabuf: Mark up onstack timer for selftests Using index info to reconstruct a base tree... M

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [PATCHv2,1/2] fs: export put_filesystem()

== Series Details == Series: series starting with [PATCHv2,1/2] fs: export put_filesystem() URL : https://patchwork.freedesktop.org/series/65478/ State : success == Summary == CI Bug Log - changes from CI_DRM_6748 -> Patchwork_14102

Re: [Intel-gfx] [PATCH] drm/i915: disable set/get_tiling ioctl on gen12+

Quoting Daniel Vetter (2019-08-20 18:06:31) > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never > supported any of the fancy new tiling formats, which means userspace > also stopped using the magic side-channel this provides. > > This would totally break a lot of the igts,

Re: [Intel-gfx] [PATCH v2 05/40] drm/i915/psr: Make PSR registers relative to transcoders

On Sat, Aug 17, 2019 at 02:38:27AM -0700, Lucas De Marchi wrote: From: José Roberto de Souza PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [PATCHv2,1/2] fs: export put_filesystem()

== Series Details == Series: series starting with [PATCHv2,1/2] fs: export put_filesystem() URL : https://patchwork.freedesktop.org/series/65478/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9be2a741432b fs: export put_filesystem() -:23: WARNING:NO_AUTHOR_SIGN_OFF: Missing

[Intel-gfx] ✗ Fi.CI.IGT: failure for mmu notifier debug annotations/checks

== Series Details == Series: mmu notifier debug annotations/checks URL : https://patchwork.freedesktop.org/series/65465/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14095_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/dp: stylistic cleanup around hdcp2_msg_data

== Series Details == Series: series starting with [1/5] drm/i915/dp: stylistic cleanup around hdcp2_msg_data URL : https://patchwork.freedesktop.org/series/65481/ State : success == Summary == CI Bug Log - changes from CI_DRM_6749 -> Patchwork_14103

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/gtt: Relax pd_used assertion

== Series Details == Series: series starting with [1/6] drm/i915/gtt: Relax pd_used assertion URL : https://patchwork.freedesktop.org/series/65486/ State : failure == Summary == Applying: drm/i915/gtt: Relax pd_used assertion Using index info to reconstruct a base tree... M

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: disable set/get_tiling ioctl on gen12+

== Series Details == Series: drm/i915: disable set/get_tiling ioctl on gen12+ URL : https://patchwork.freedesktop.org/series/65495/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7f41e4bbdc3a drm/i915: disable set/get_tiling ioctl on gen12+ -:48: WARNING:NO_AUTHOR_SIGN_OFF:

Re: [Intel-gfx] [PATCH] drm/i915: disable set/get_tiling ioctl on gen12+

Quoting Daniel Vetter (2019-08-20 20:06:19) > On Tue, Aug 20, 2019 at 8:55 PM Chris Wilson wrote: > > > > Quoting Daniel Vetter (2019-08-20 18:06:31) > > > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never > > > supported any of the fancy new tiling formats, which means

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Be defensive when starting vma activity

== Series Details == Series: drm/i915: Be defensive when starting vma activity URL : https://patchwork.freedesktop.org/series/65471/ State : success == Summary == CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14098_full Summary

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: disable set/get_tiling ioctl on gen12+ (rev2)

== Series Details == Series: drm/i915: disable set/get_tiling ioctl on gen12+ (rev2) URL : https://patchwork.freedesktop.org/series/65495/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14110 Summary

Re: [Intel-gfx] [PATCH v2 07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall

On Tue, 2019-08-20 at 13:29 -0700, Lucas De Marchi wrote: > On Sat, Aug 17, 2019 at 02:38:29AM -0700, Lucas De Marchi wrote: > > From: José Roberto de Souza > > > > No need to unmask PSR interrutpion if PSR is not enabled, better > > move > > the call to intel_psr_enable_source(). > > > > Cc:

Re: [Intel-gfx] [PATCH] drm/i915: Do not create a new max_bpc prop for MST connectors

Reviewed-by: Lyude Paul On Tue, 2019-08-20 at 19:16 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > We're not allowed to create new properties after device registration > so for MST connectors we need to either create the max_bpc property > earlier, or we reuse one we already have. Let's

[Intel-gfx] [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions

Refactor instdone loops to use the new intel_sseu_has_subslice function. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-

[Intel-gfx] [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info

When setting up subslice_mask, instead of operating on the slice array directly, use a local variable to start bits per slice, then use this to set the per slice array in one step. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/intel_device_info.c | 49 +--- 1 file

[Intel-gfx] [PATCH 04/11] drm/i915: Add EU stride runtime parameter

Add a new SSEU runtime parameter, eu_stride, which is used to mirror the userspace concept of a range of EUs per subslice. This patch simply adds the parameter and updates usage in the QUERY_TOPOLOGY_INFO handler. Signed-off-by: Stuart Summers Reviewed-by: Chris Wilson ---

[Intel-gfx] [PATCH 01/11] drm/i915: Use variable for debugfs device status

Use a local variable to find SSEU runtime information in various debugfs functions. v2: Remove extra line breaks per feedback from Chris Signed-off-by: Stuart Summers Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 26 +++--- 1 file changed, 11

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev4)

Sent the patch again with CI tag, to check the results. Anusha > -Original Message- > From: Navare, Manasi D > Sent: Monday, August 19, 2019 4:06 PM > To: intel-gfx@lists.freedesktop.org > Cc: Srivatsa, Anusha > Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp/dsc: Add Support

[Intel-gfx] [CI] drm/dp/dsc: Add Support for all BPCs supported by TGL

DSC engine on ICL supports only 8 and 10 BPC as the input BPC. But DSC engine in TGL supports 8, 10 and 12 BPC. Add 12 BPC support for DSC while calculating compression configuration. v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC and use the value directly.(More such defines can be

Re: [Intel-gfx] [PATCH] drm/i915/uc: define GuC and HuC FWs for EHL

On Mon, Aug 19, 2019 at 06:23:27PM -0700, Daniele Ceraolo Spurio wrote: > First uc firmware release for EHL. > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Matt Roper > Cc: Anusha Srivatsa > Cc: Michal Wajdeczko The new firmwares load properly with this patch. Tested-by: Matt Roper

[Intel-gfx] ✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev4)

== Series Details == Series: Tiger Lake batch 3 (rev4) URL : https://patchwork.freedesktop.org/series/65290/ State : failure == Summary == Applying: drm/i915/tgl: disable DDIC Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to

[Intel-gfx] [PATCH v8 1/3] drm/i915/psr: Make PSR registers relative to transcoders

PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and using it makes more difficult for people with an PSR register address or PSR register name from from

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement TGL DisplayPort training sequence

On Tue, Aug 20, 2019 at 03:01:38PM -0700, José Roberto de Souza wrote: > On TGL some registers moved from DDI to transcoder and the > DisplayPort training sequence has a separate BSpec page. > > I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but > it was becoming really hard to

[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65509/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14114 Summary ---

[Intel-gfx] [PATCH v8 2/3] drm/i915: Add transcoder restriction to PSR2

According to PSR2_CTL definition in BSpec there is only one instance of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on TRANSCODER_EDP while on TGL PSR2 is only supported by TRANSCODER_A. Since BDW PSR is allowed on any port, but we need to restrict by transcoder. v8:

[Intel-gfx] [PATCH v8 3/3] drm/i915: Do not unmask PSR interruption in IRQ postinstall

No need to unmask PSR interrutpion if PSR is not enabled, better move the call to intel_psr_enable_source(). v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH 02/11] drm/i915: Add function to set SSEU info per platform

Add a new function to allow each platform to set maximum slice, subslice, and EU information to reduce code duplication. Signed-off-by: Stuart Summers Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_sseu.c | 8 + drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++

[Intel-gfx] [PATCH 06/11] drm/i915: Add function to set subslices

Add a new function to set a set of subslices for a given slice. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++ drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++ drivers/gpu/drm/i915/intel_device_info.c | 18 +++--- 3 files changed, 20

[Intel-gfx] [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice

Add a new function to determine whether a particular slice has a given subslice. Signed-off-by: Stuart Summers Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_sseu.h | 16 drivers/gpu/drm/i915/intel_device_info.c | 9 - 2 files changed, 20

[Intel-gfx] [PATCH 11/11] drm/i915: Expand subslice mask

Currently, the subslice_mask runtime parameter is stored as an array of subslices per slice. Expand the subslice mask array to better match what is presented to userspace through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is then calculated: slice * subslice stride + subslice

[Intel-gfx] [PATCH 00/11] Refactor to expand subslice mask (rev 2)

Currently, the subslice_mask runtime parameter is stored as an array of subslices per slice. Expand the subslice mask array to better match what is presented to userspace through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is then calculated: slice * subslice stride + subslice

[Intel-gfx] [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice

Add a new function to copy subslices for a specified slice between intel_sseu structures for the purpose of determining power-gate status. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/i915_debugfs.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice

Add a subslice stride calculation when setting subslices. This aligns more closely with the userspace expectation of the subslice mask structure. v2: Use local variable for subslice_mask on HSW and clean up a few other subslice_mask local variable changes v3: Add GEM_BUG_ON for ss_stride

[Intel-gfx] [PATCH 03/11] drm/i915: Add subslice stride runtime parameter

Add a new parameter, ss_stride, to the runtime info structure. This is used to mirror the userspace concept of subslice stride, which is a range of subslices per slice. This patch simply adds the definition and updates usage in the QUERY_TOPOLOGY_INFO handler. Signed-off-by: Stuart Summers

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative to transcoders

== Series Details == Series: series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative to transcoders URL : https://patchwork.freedesktop.org/series/65507/ State : warning == Summary == $ dim checkpatch origin/drm-tip 180c73435134 drm/i915/psr: Make PSR registers relative to

Re: [Intel-gfx] [PATCH v2 22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards

On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote: > From: Michel Thierry > > Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist). Took a look at this one today and I can at least say this register is not present at the previous location. I didn't have any luck finding a

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65509/ State : warning == Summary == $ dim checkpatch origin/drm-tip f87889b5f343 drm/i915: Use variable for debugfs device status c0f971db0755 drm/i915: Add function to set

[Intel-gfx] [PATCH v2] drm/i915/tgl: Implement TGL DisplayPort training sequence

On TGL some registers moved from DDI to transcoder and the DisplayPort training sequence has a separate BSpec page. I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but it was becoming really hard to follow, so a new and cleaner function for TGL was added with comments of all

Re: [Intel-gfx] [PATCH v8 3/3] drm/i915: Do not unmask PSR interruption in IRQ postinstall

On Tue, Aug 20, 2019 at 03:33:25PM -0700, Jose Souza wrote: No need to unmask PSR interrutpion if PSR is not enabled, better move the call to intel_psr_enable_source(). v2: Renamed intel_psr_irq_control() to psr_irq_control() (Lucas) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative to transcoders

== Series Details == Series: series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative to transcoders URL : https://patchwork.freedesktop.org/series/65507/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14112

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev5)

== Series Details == Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev5) URL : https://patchwork.freedesktop.org/series/63526/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14113 Summary

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev 2)

== Series Details == Series: Refactor to expand subslice mask (rev 2) URL : https://patchwork.freedesktop.org/series/65509/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Use variable for debugfs device status Okay! Commit: drm/i915: Add

[Intel-gfx] [PATCH v2] drm/i915: Move vgpu balloon info into i915_virtual_gpu struct

vgpu ballon info consists of four drm_mm_node which is used to reserve ggtt space, then linux guest won't use these reserved ggtt space. Each vgpu has its own ballon info, so move ballon info into i915_virtual_gpu structure. v2: Fix dim PARENTHESIS_ALIGNMENT check warning Signed-off-by: Xiong

Re: [Intel-gfx] [PATCH v8 2/3] drm/i915: Add transcoder restriction to PSR2

On 2019-08-20 at 15:33:24 -0700, José Roberto de Souza wrote: > According to PSR2_CTL definition in BSpec there is only one instance > of PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 > on TRANSCODER_EDP while on TGL PSR2 is only supported by > TRANSCODER_A. > > Since BDW PSR

Re: [Intel-gfx] [PATCH v8 1/3] drm/i915/psr: Make PSR registers relative to transcoders

On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote: > PSR registers are a mess, some have the full address while others just > have the additional offset from psr_mmio_base. > > For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + > 0x800 and using it makes more difficult

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Relax assertion for pt_used

== Series Details == Series: drm/i915/gtt: Relax assertion for pt_used URL : https://patchwork.freedesktop.org/series/65518/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14116 Summary ---

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Lower cdclk for sub 4k resolutions

== Series Details == Series: drm/i915/tgl: Lower cdclk for sub 4k resolutions URL : https://patchwork.freedesktop.org/series/65475/ State : success == Summary == CI Bug Log - changes from CI_DRM_6748_full -> Patchwork_14100_full Summary

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest

On 2019.08.20 13:46:17 +0800, Xiong Zhang wrote: > The following call trace may exist in linux guest dmesg when guest i915 > driver is unloaded. > [ 90.776610] [drm:vgt_deballoon_space.isra.0 [i915]] deballoon space: range > [0x0 - 0x0] 0 KiB. > [ 90.776621] BUG: unable to handle kernel NULL

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Don't deballoon unused ggtt drm_mm_node in linux guest (rev2) URL : https://patchwork.freedesktop.org/series/65450/ State : success == Summary == CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14115

[Intel-gfx] [PATCH] drm/i915/gtt: Relax assertion for pt_used

When inserting the final level PTE, we check that we are not overflowing the page table (checking that pt_used does not exceed the size of the table). However, we have to allow for every other PTE to be pinned by a simultaneous removal thread (as on remove we bump the pt_used counter before

[Intel-gfx] linux-next: manual merge of the iommu tree with the drm-misc tree

Hi all, Today's linux-next merge of the iommu tree got a conflict in: drivers/gpu/drm/panfrost/panfrost_mmu.c between commit: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations") from the drm-misc tree and commit: a2d3a382d6c6 ("iommu/io-pgtable: Pass struct

Re: [Intel-gfx] [PATCH] drm/i915: Do not create a new max_bpc prop for MST connectors

On Tue, 2019-08-20 at 19:16 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > We're not allowed to create new properties after device registration > so for MST connectors we need to either create the max_bpc property > earlier, or we reuse one we already have. Let's do the latter > apporach

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