Hi,
On 9/9/19 7:00 PM, Chris Wilson wrote:
Despite the widespread and complete failure of Broadwell integrated
graphics when DMAR is enabled, known over the years, we have never been
able to root cause the issue. Instead, we let the failure undermine our
confidence in the iommu system itself
On Tue, Sep 10, 2019 at 09:32:45AM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-09-10 08:39:31)
> > On Mon, Sep 09, 2019 at 11:55:35PM +0100, Chris Wilson wrote:
> > > If the display is inactive, we need not worry about the gpu reset
> > > clobbering the display!
> > >
> > >
On Mon, 09 Sep 2019, Manasi Navare wrote:
> On Thu, Sep 05, 2019 at 11:03:12AM +0530, Nautiyal, Ankit K wrote:
>> Hi,
>>
>> I was able to get 5K HPz27q 317b monitor for some time. Below are the
>> observation on HPz27q Monitor with two DP cables connected to a KBL machine.
>>
>> *General
On Sun, 08 Sep 2019, Manasi Navare wrote:
> This patch series addresses all review comments and now the enable and
> disable paths follow the method of obtaining slave states from master
> and updating master-slaves in correct order during master modeset.
Main high level question: what does it
Chris Wilson writes:
> During reset, we try to ensure no forward progress of the CS prior to
> the reset by setting the STOP_RING bit in RING_MI_MODE. Since gen9, this
> register is context saved and do we end up in the odd situation where we
> save the STOP_RING bit and so try to stop the
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14350_full
Summary
---
On Tue, Sep 10, 2019 at 11:55:40PM +, Patchwork wrote:
> == Series Details ==
>
> Series: cdclk consolidation and rework for BXT-TGL (rev6)
> URL : https://patchwork.freedesktop.org/series/66365/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6861_full ->
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write
URL : https://patchwork.freedesktop.org/series/66502/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14349_full
On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
Hi Imre ,
Thanks for review, could you please provide your response on below
comments.
> On Sat, Sep 07, 2019 at 10:44:42PM +0530, Anshuman Gupta wrote:
> > DC3CO is useful power state, when DMC detects PSR2 idle frame
> > while an active video
Quoting Mika Kuoppala (2019-09-10 10:54:43)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2019-09-10 10:31:05)
> >> Chris Wilson writes:
> >>
> >> > During reset, we try to ensure no forward progress of the CS prior to
> >> > the reset by setting the STOP_RING bit in RING_MI_MODE. Since
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14339
Chris Wilson writes:
> Be paranoid and make sure we flush any and all writes out of the WCB
> before performing the UC mmio to update the RING_TAIL. (An UC write
> should itself be enough to do the flush, hence the paranoia here.) Quite
> infrequently, we see problems where the GPU seems to
On Tue, 10 Sep 2019 at 13:10, Chris Wilson wrote:
>
> Currently, if there is time remaining before the start of the loop, we
> do one full iteration over many possible different chunks within the
> object. A full loop may take 50+s (depending on speed of indirect GTT
> mmapings) and we try
On Fri, Sep 06, 2019 at 05:21:42PM -0700, Matt Roper wrote:
> When reading out the BIOS-programmed cdclk state, let's make sure that
> the cdclk value is on the valid list for the platform, ensure that the
> VCO matches the cdclk, and ensure that the CD2X divider was set
> properly.
Reviewed-by:
== Series Details ==
Series: drm/i915/tgl: Keep forcewake always for now
URL : https://patchwork.freedesktop.org/series/66483/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14338
Summary
---
On Tue, Sep 10, 2019 at 3:34 AM Mun, Gwan-gyeong
wrote:
>
> On Sat, 2019-09-07 at 21:43 -0400, Ilia Mirkin wrote:
> > On Sat, Sep 7, 2019 at 7:20 PM Mun, Gwan-gyeong
> > wrote:
> > > On Fri, 2019-09-06 at 09:24 -0400, Ilia Mirkin wrote:
> > > > On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
> > >
From: Tvrtko Ursulin
Code in i915_gem_init_hw is all about GT init so move it to intel_gt.c
renaming to intel_gt_init_hw.
Existing intel_gt_init_hw is renamed to intel_gt_init_hw_early since it
is currently called from driver probe.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris
From: Tvrtko Ursulin
Timelines live in struct intel_gt so make wait_for_timelines take
exactly what it needs.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
From: Tvrtko Ursulin
Both in the container_of and getting to gt->awake there is no need to go
via i915 since both the wakeref and awake are members of gt.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +++---
1 file changed, 3
From: Tvrtko Ursulin
A few patches left hanging since late July. First one old in spirit but adjusted
and renamed and the rest update for latest drm-tip.
Happy to receive thoughts on whether this cleanup makes sense.
Cc: Andi Shyti
Cc: Chris Wilson
Tvrtko Ursulin (4):
drm/i915: Move GT
From: Tvrtko Ursulin
These notifications operate on intel_gt so make the code take what it
needs.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> Add an atomic counter and always take the spinlock around the pin/unpin
> events, so that we can perform the list manipulation concurrently.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> In preparation for reducing struct_mutex stranglehold around the vm,
> make the vma.flags atomic so that we can acquire a pin on the vma
> atomically before deciding if we need to take the mutex.
>
> Signed-off-by: Chris Wilson
Reviewed-by:
On Mon, 2 Sep 2019 at 05:03, Chris Wilson wrote:
>
> As we remove the struct_mutex protection from around the vma pinning,
> counters need to be atomic and aware that there may be multiple threads
> simultaneously active.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
== Series Details ==
Series: drm/i915: Use a high priority wq for nonblocking plane updates
URL : https://patchwork.freedesktop.org/series/66485/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14340_full
Quoting Patchwork (2019-09-10 18:24:49)
> * igt@i915_selftest@live_gem_contexts:
> - {fi-tgl-u}: NOTRUN -> [DMESG-FAIL][3]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14346/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
Doesn't that look familiar. Same
On Tue, 10 Sep 2019 at 17:17, Chris Wilson wrote:
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Acked-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4144570a45a2 drm/i915: Move GT init to intel_gt.c
-:89: WARNING:AVOID_BUG: Avoid crashing the kernel - try using
Quoting Tvrtko Ursulin (2019-09-10 15:38:21)
> From: Tvrtko Ursulin
>
> Timelines live in struct intel_gt so make wait_for_timelines take
> exactly what it needs.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
> Cc: Chris Wilson
I've deleted this code, fwiw, merged it with request
Quoting Patchwork (2019-09-10 18:24:49)
> == Series Details ==
>
> Series: drm/i915/tgl: Disable rc6 for debugging (rev2)
> URL : https://patchwork.freedesktop.org/series/66492/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14346
>
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860_full -> Patchwork_14339_full
On 9/9/19 12:28 PM, Anusha Srivatsa wrote:
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Update the versions of huc being loaded of the
Quoting Matthew Auld (2019-09-10 20:56:48)
> On Tue, 10 Sep 2019 at 17:17, Chris Wilson wrote:
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=111593
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> Acked-by: Matthew Auld
Filled in the blurb and pushed. Let's see how
On Tue, Sep 10, 2019 at 11:46:20AM +0200, Jean Delvare wrote:
> Hi Ville,
>
> On Mon, 2 Sep 2019 16:15:46 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's make cea_db_offsets() a bit more convenient to use by
> > setting the start/end offsets to zero whenever the data block
>
On Tue, 10 Sep 2019 12:48:42 +0300, Ville Syrjälä wrote:
> On Tue, Sep 10, 2019 at 11:46:20AM +0200, Jean Delvare wrote:
> > Hi Ville,
> >
> > On Mon, 2 Sep 2019 16:15:46 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Let's make cea_db_offsets() a bit more convenient to
Currently the property docs don't specify whether it's okay for two planes to
have the same zpos value and what user-space should expect in this case.
The rule mentionned in the past was to disambiguate with object IDs. However
some drivers break this rule (that's why the ordering is documented
On 10-Sep-19 3:57 PM, Jani Nikula wrote:
On Mon, 09 Sep 2019, Swati Sharma wrote:
In this patch series, added state checker to validate gamma lut values
for cherryview and i965 platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which
Currently, if there is time remaining before the start of the loop, we
do one full iteration over many possible different chunks within the
object. A full loop may take 50+s (depending on speed of indirect GTT
mmapings) and we try separately with LINEAR, X and Y -- at which point
igt times out. If
== Series Details ==
Series: drm/i915/selftests: Tighten the timeout testing for partial mmaps
URL : https://patchwork.freedesktop.org/series/66484/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8b28c802b06b drm/i915/selftests: Tighten the timeout testing for partial mmaps
Quoting Mika Kuoppala (2019-09-10 12:35:47)
> Forcewake handling is a prime suspect now. Keep ref
> always on tgl to test the theory and reveal the coverage.
>
> Testcase: igt/gem_sync
> Cc: Chris Wilson
> Suggested-by: Chris Wilson
> Signed-off-by: Mika Kuoppala
Gets us as far as reload,
On Fri, Aug 09, 2019 at 01:53:43PM +0100, Chris Wilson wrote:
> Quoting Martin Wilck (2019-08-09 13:41:42)
> > This happened to me today, running kernel 5.3.0-rc3-1.g571863b-default
> > (5.3-rc3 with just a few patches on top), after starting a KVM virtual
> > machine. The X screen was frozen.
== Series Details ==
Series: series starting with drm/i915: Force compilation with intel-iommu for
CI validation (rev2)
URL : https://patchwork.freedesktop.org/series/66487/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f0df04b62a3b drm/i915: Force compilation with
Quoting Ville Syrjala (2019-09-10 13:13:47)
> From: Ville Syrjälä
>
> system_unbound_wq can't keep up sometimes and we get dropped frames.
> Switch to a high priority variant.
>
> Reported-by: Heinrich Fink
> Tested-by: Heinrich Fink
> Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
On Fri, Sep 06, 2019 at 05:21:43PM -0700, Matt Roper wrote:
> The BXT and CNL functions were already basically identical, whereas
> ICL's function tried to do its own sanitization rather than calling
> bxt_sanitize_cdclk.
>
> This should actually fix a bug in our ICL initialization where it would
On Mon, 09 Sep 2019 21:28:00 +0200, Anusha Srivatsa
wrote:
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
above commit message (and patch title) is little misleading as updating
a macro is
Forcewake handling is a prime suspect now. Keep ref
always on tgl to test the theory and reveal the coverage.
Testcase: igt/gem_sync
Cc: Chris Wilson
Suggested-by: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem.c | 5 -
1 file changed, 4 insertions(+), 1
On Fri, Sep 06, 2019 at 05:21:36PM -0700, Matt Roper wrote:
> Aside from a few minor register changes and some different clock values,
> cdclk design hasn't changed much since gen9lp. Let's consolidate the
> handlers for bxt, cnl, and icl to keep the codeflow consistent.
>
> Also, while we're at
On Fri, Sep 06, 2019 at 05:21:39PM -0700, Matt Roper wrote:
> The CNL variant of this function is identical to the BXT variant aside
> from not needing to handle SSA precharge.
>
> Cc: Ville Syrjälä
> Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
> ---
>
== Series Details ==
Series: drm/i915/execlists: Clear STOP_RING bit on reset (rev2)
URL : https://patchwork.freedesktop.org/series/66473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6857_full -> Patchwork_14336_full
== Series Details ==
Series: drm/i915: Use a high priority wq for nonblocking plane updates
URL : https://patchwork.freedesktop.org/series/66485/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14340
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 00786a142ff0..c5c00cad6ba1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++
On Wed, Aug 21, 2019 at 03:32:19PM +0200, Maarten Lankhorst wrote:
> We cannot switch between HQ and normal mode on GLK+, so only
> add planes on platforms where it makes sense.
>
> We could probably restrict it even more to only add when scaler
> users toggles between 1 and 2, but lets just
Hi Ville,
On Mon, 2 Sep 2019 16:15:46 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's make cea_db_offsets() a bit more convenient to use by
> setting the start/end offsets to zero whenever the data block
> collection isn't present. This makes it safe for the caller
> to blindly
Chris Wilson writes:
> Icelake hit an issue where it missed reporting a completion event and
> instead jumped straight to a idle->active event (skipping over the
> active->idle and not even hitting the lite-restore preemption).
>
> 661497511us : process_csb: rcs0 cs-irq head=11, tail=0
>
== Series Details ==
Series: drm: two planes with the same zpos have undefined ordering
URL : https://patchwork.freedesktop.org/series/66480/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b8f1c2a9415 drm: two planes with the same zpos have undefined ordering
-:6:
On Sat, Sep 07, 2019 at 09:05:00PM -0700, Matt Roper wrote:
> The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
> dividers in an easy-to-read table for most recent platforms. We've been
> translating the data from that table into platform-specific code logic,
> but it's easy to
Hi Ville,
On Mon, 2 Sep 2019 16:15:45 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> CEA ext block revisions 1 and 2 do not contain the data block
> collection. Instead that section of the extension block is
> marked as reserved for 8 byte timing descriptors. Revision 3
> changed it to
Quoting Mika Kuoppala (2019-09-10 10:31:05)
> Chris Wilson writes:
>
> > During reset, we try to ensure no forward progress of the CS prior to
> > the reset by setting the STOP_RING bit in RING_MI_MODE. Since gen9, this
> > register is context saved and do we end up in the odd situation where we
Chris Wilson writes:
> As soon as we re-enable the various functions within the HW, they may go
> off and read data via a GGTT offset. Hence, if we have not yet restored
> the GGTT PTE before then, they may read and even *write* random locations
> in memory.
>
> Detected by DMAR faults during
== Series Details ==
Series: drm: two planes with the same zpos have undefined ordering
URL : https://patchwork.freedesktop.org/series/66480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6860 -> Patchwork_14337
Summary
On Fri, Sep 06, 2019 at 05:21:41PM -0700, Matt Roper wrote:
> With all of the cdclk function consolidation, we can cut down on a lot
> of platform if/else logic by creating a vfunc that's initialized at
> startup.
Reviewed-by: Ville Syrjälä
>
> Cc: Ville Syrjälä
> Signed-off-by: Matt Roper
>
On Fri, Sep 06, 2019 at 05:21:40PM -0700, Matt Roper wrote:
> The uninitialize flow is the same on all of these platforms, aside from
> calculating a different frequency level.
>
> Cc: Ville Syrjälä
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 48
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 00786a142ff0..06709dd6a2e0 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++
---
drivers/iommu/intel-iommu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 34f6a3d93ae2..c98cdfd91691 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -439,8 +439,6 @@ static int __init
Despite the widespread and complete failure of Broadwell integrated
graphics when DMAR is enabled, known over the years, we have never been
able to root cause the issue. Instead, we let the failure undermine our
confidence in the iommu system itself when we should be pushing for it to
be always
Chris Wilson writes:
> Despite the widespread and complete failure of Broadwell integrated
> graphics when DMAR is enabled, known over the years, we have never been
> able to root cause the issue. Instead, we let the failure undermine our
> confidence in the iommu system itself when we should be
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-09-10 10:31:05)
>> Chris Wilson writes:
>>
>> > During reset, we try to ensure no forward progress of the CS prior to
>> > the reset by setting the STOP_RING bit in RING_MI_MODE. Since gen9, this
>> > register is context saved and do we end up
On Mon, 09 Sep 2019, Swati Sharma wrote:
> In this patch series, added state checker to validate gamma lut values
> for cherryview and i965 platforms. It's extension of the
> patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
> which enabled the basic infrastructure and
On Mon, 9 Sep 2019 at 12:00, Chris Wilson wrote:
>
> Being a "low-level" test, we opt to bypass the normal bind/unbind hooks
> for the lower level insert_entries/clear_range. For ggtt, the
> bind/unbind hooks provide the runtime wakeref and so we must also handle
> this in exercising the low
From: Ville Syrjälä
system_unbound_wq can't keep up sometimes and we get dropped frames.
Switch to a high priority variant.
Reported-by: Heinrich Fink
Tested-by: Heinrich Fink
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
On Fri, Sep 06, 2019 at 05:21:38PM -0700, Matt Roper wrote:
> We'd previously combined ICL/TGL logic into the cnl_set_cdclk function,
> but BXT is pretty similar as well. Roll the cnl/icl/tgl logic back into
> the bxt function; the only things we really need to handle separately
> are punit
On Mon, 2019-09-09 at 15:35 -0700, Rodrigo Vivi wrote:
> On Mon, Sep 09, 2019 at 02:54:59PM -0700, Vetter, Daniel wrote:
> > On Mon, 2019-09-09 at 10:24 -0700, Rodrigo Vivi wrote:
> > > Hi guys,
> > >
> > > On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
> > > > Hi,
> > > >
> > > >
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14342_full
Summary
---
On 9/10/19 2:35 PM, Srivatsa, Anusha wrote:
-Original Message-
From: Ceraolo Spurio, Daniele
Sent: Tuesday, September 10, 2019 2:05 PM
To: Srivatsa, Anusha ; intel-
g...@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
On 9/9/19 12:28 PM,
This allows userspace to use "legacy" mode for push constants, where
they are committed at 3DPRIMITIVE or flush time, rather than being
committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
both use the "legacy" behavior - only Gen9 works in the "new" way.
Conflating push
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
Cc: Matthew
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write
URL : https://patchwork.freedesktop.org/series/66502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14349
Summary
On 9/10/19 3:46 PM, Robert M. Fosha wrote:
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other
== Series Details ==
Series: drm/i915/tgl: Disable rc6 for debugging (rev2)
URL : https://patchwork.freedesktop.org/series/66492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14346_full
Summary
== Series Details ==
Series: drm/i915: Make shrink/unshrink be atomic
URL : https://patchwork.freedesktop.org/series/66501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6862_full -> Patchwork_14347_full
Summary
---
Add an atomic counter and always take the spinlock around the pin/unpin
events, so that we can perform the list manipulation concurrently.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 3 +-
On Tue, Sep 10, 2019 at 12:20:05PM +0300, Jani Nikula wrote:
> On Mon, 09 Sep 2019, Manasi Navare wrote:
> > On Thu, Sep 05, 2019 at 11:03:12AM +0530, Nautiyal, Ankit K wrote:
> >> Hi,
> >>
> >> I was able to get 5K HPz27q 317b monitor for some time. Below are the
> >> observation on HPz27q
== Series Details ==
Series: series starting with drm/i915: Force compilation with intel-iommu for
CI validation (rev2)
URL : https://patchwork.freedesktop.org/series/66487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14341_full
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14350
Summary
---
== Series Details ==
Series: HuC Updates (rev2)
URL : https://patchwork.freedesktop.org/series/66504/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d870e2a94ef8 drm/i915/uc: Update GuC and HuC firmware naming convention
9b0da66fbfad HAX: force enable_guc=2
-:7:
== Series Details ==
Series: drm/ttm: make ttm bo a gem bo subclass (rev5)
URL : https://patchwork.freedesktop.org/series/64701/
State : failure
== Summary ==
Applying: drm/ttm: add gem base object
Using index info to reconstruct a base tree...
M include/drm/ttm/ttm_bo_api.h
Falling
== Series Details ==
Series: drm/i915: Make shrink/unshrink be atomic
URL : https://patchwork.freedesktop.org/series/66501/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6862 -> Patchwork_14347
Summary
---
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL (rev6)
URL : https://patchwork.freedesktop.org/series/66365/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861_full -> Patchwork_14345_full
Summary
This allows userspace to use "legacy" mode for push constants, where
they are committed at 3DPRIMITIVE or flush time, rather than being
committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
both use the "legacy" behavior - only Gen9 works in the "new" way.
Conflating push
On 9/9/19 11:06 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-09-10 01:59:38)
On 9/9/19 3:55 PM, Chris Wilson wrote:
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Tuesday, September 10, 2019 2:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
>
>
>
> On 9/9/19 12:28 PM, Anusha Srivatsa wrote:
> >
The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f:
linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09
04:22:42 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware ehl_huc
for you to fetch changes
Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.
The current convention being:
_uc_..patch.bin
Update the versions of HuC being loaded of the platforms.
SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++
== Series Details ==
Series: HuC Updates (rev2)
URL : https://patchwork.freedesktop.org/series/66504/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14351
Summary
---
**SUCCESS**
No regressions
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2 (rev2)
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863 -> Patchwork_14352
Summary
---
On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> > On Sun, 08 Sep 2019, Manasi Navare wrote:
> > > This patch series addresses all review comments and now the enable and
> > > disable paths follow the method of
On Sat, Sep 07, 2019 at 12:21:11AM -0700, Dhinakaran Pandiyan wrote:
> Gen-12 display decompression operates on Y-tiled compressed main surface.
> The CCS is linear and has 4 bits of metadata for each main surface cache
> line pair, a size ratio of 1:256. Gen-12 display decompression is
>
On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote:
> On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding
> wrote:
> >
> > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> > > On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> > > >
> > > > Hi,
> > > >
> > > > > > Changing
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2
URL : https://patchwork.freedesktop.org/series/66503/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31adb9f5fd42 drm/i915: Whitelist COMMON_SLICE_CHICKEN2
-:29: ERROR:MISSING_SIGN_OFF: Missing
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